NRF9E5 NORDIC SEMICONDUCTOR, NRF9E5 Datasheet - Page 85

• Manufacturer Part Number: NRF9E5
• Description: TRX, 430-928MHZ, MCU/ADC/PWM, SMD
• Manufacturer: NORDIC SEMICONDUCTOR

Specifications of NRF9E5

• Receiving Current: 12.5mA
• Transmitting Current: 30mA
• Data Rate: 50Kbps
• Frequency Range: 430MHz To 928MHz
• Modulation Type: GFSK
• Rf Ic Case Style: QFN
• No. Of Pins: 32
• Supply Voltage Range: 1.9V To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
The lack of open drain ports on nRF9E5 makes it a programmer responsibility to control
the direction of the RXD pin.
The serial mode 0 baud rate is either CPU_clk/12 or CPU_clk/4, depending on the state
of the SM2. When SM2 = 0, the baud rate is CPU_clk/12; when SM2 = 1, the baud rate
is CPU_clk/4.
Mode 0 operation is identical to the standard 8051. Data transmission begins when an
instruction writes to the SBUF SFR. The UART shifts the data out, LSB first, at the
selected baud rate, until the 8-bit value has been shifted out.
Mode 0 data reception begins when the REN bit is set and the RI bit is cleared in the
corresponding SCON SFR. The shift clock is activated and the UART shifts data in on
each rising edge of the shift clock until eight bits have been received. One machine cycle
after the 8
the RI bit.
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone [phone] - Fax [phone]
Revision: 1.3
Figure 26 Serial Port Mode 0 transmit timing for high-speed (CPU_clk/4) operation.
Figure 27 Serial Port Mode 0 transmit timing for high-speed (CPU_clk/4) operation.
Figure 24 Serial Port Mode 0 receive timing for low-speed (CPU_clk/12) operation.
Figure 25 Serial Port Mode 0 receive timing for high-speed (CPU_clk/4) operation.
RXD
TXD
th
RXD
TXD
RI
TI
RXD
TXD
bit is shifted in, the RI bit is set and reception stops until the software clears
RI
TI
RXD
TXD
RI
TI
RI
TI
D0
D0
D0
D0
D1
D1
D1
D1
D2
D2
D2
D2
Page 85 of 108
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
D7
June 2006