CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 113
![16-Bit Microcontroller IC](/photos/19/4/190456/3833527_sml.gif)
CR16MCS9VJE8
Manufacturer Part Number
CR16MCS9VJE8
Description
16-Bit Microcontroller IC
Manufacturer
National Semiconductor
Datasheet
1.CR16MCS9VJE8.pdf
(156 pages)
Specifications of CR16MCS9VJE8
Controller Family/series
CR16X
Core Size
16 Bit
Program Memory Size
64K X 8 Flash
Digital Ic Case Style
PQFP
No. Of Pins
80
Mounting Type
Surface Mount
Clock Frequency
25MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CR16MCS9VJE8
Manufacturer:
ON
Quantity:
8 917
Company:
Part Number:
CR16MCS9VJE8-CBB
Manufacturer:
ON
Quantity:
846
Company:
Part Number:
CR16MCS9VJE8-CBC
Manufacturer:
ON
Quantity:
109
Company:
Part Number:
CR16MCS9VJE8-CBD
Manufacturer:
ON
Quantity:
17
Company:
Part Number:
CR16MCS9VJE8-CBE
Manufacturer:
ON
Quantity:
1 950
GM[28:15]
GM[14:0]
For all GMSKB and GMSKX register bits, the following ap-
plies:
When an extended frame is received from the CAN bus, all
Global Mask bits GM28 through GM0, IDE, RTR and XRTR
are used to mask the incoming message.
During the reception of standard frames only the Global
Mask bits GM28 to GM18, RTR and IDE are utilized.
20.9.11 Basic Mask Registers (BMSK — BMSKB and
The two registers BMSKB and BMSKX allow to mask the
buffer 14, or “don’t care” the incoming extended/standard
identifier bits, RTR/XRTR and IDE. Throughout this docu-
ment, the two 16-bit registers BMSKB and BMSKX are refer-
enced to as a 32-bit register BMSK.
BM[28:15]
15
extended frame
standard frame
15
15
Global Mask
— “0” is the incoming identifier bit must match the corre-
— “1” accept “1” or “0” (“don’t care”) of the incoming ID bit
a.
sponding bit in the message buffer identifier register.
independent from the corresponding bit in the mes-
sage buffer ID registers. The corresponding ID bit in
the message buffer will be overwritten by the incoming
identifier bits.
the RTR bit has a different position in standard and
extended frames
— for standard frames the GMSK_RTR bit is used to
mask this bit
— for extended frames the GMSK_XRTR bit is used to
mask this
GM[28:18]
BMSKX)
BM[28:18]
The following are the bits for the GMSKB reg-
ister.
The following are the bits for the GMSKX reg-
ister.
The following are the bits for the BMSKB regis-
ter.
bit
GM[28:18] RTR
ID[28:18]
ID[10:0]
GM[14:0]
5
5
RTR
r/w
r/w
r/w
0
0
SRR
0
4
RTR
RTR
4
a
IDE
IDE
IDE
IDE
3
IDE
3
GM[17:0]
2
ID[17:0]
GM[17:15]
2
BM[17:15]
unused
1
XRTR
XRTR
RTR
0
0
0
113
BM[14:0]
For all BMSKB and BMSKX register bits the following ap-
plies:
When an extended frame is received from the CAN bus all
Basic Mask bits BM28 through BM0, IDE, RTR and XRTR
are used to mask the incoming message.
During the reception of standard frames only the Basic Mask
bits BM28 to BM18, RTR and IDE are utilized.
20.9.12 CAN Interrupt Enable Register (CIEN)
The CAN Interrupt Enable (CIEN) register enables the trans-
mit/receive interrupts of the message buffers 0 through 14 as
well as the CAN Error Interrupt.
EIEN
IEN[14:0]
extended frame ID[28:18]
standard frame
Basic Mask
— “0” incoming identifier bit must match the correspond-
— “1” accept “1” or “0” (“don’t care”) of the incoming ID bit
15
a. the RTR bit has a different position in standard and
ing bit in the message buffer identifier register.
independent from the corresponding bit in the mes-
sage buffer ID registers. The corresponding ID bit in
the message buffer will be overwritten by the incoming
identifier bits.
EIEN
extended frames
— for standard frames the BMSK_RTR bit is used to
mask this bit
— for extended frames the BMSK_XRTR bit is used to
mask this bit
15
BM[14:0]
The following are the bits for the BMSKX regis-
ter.
Error Interrupt Enable. This bit allows the
CR16CAN to interrupt the CPU if any kind of
CAN receive/transmit errors are detected. This
means any error status change in the error
counter registers REC/TEC is able to generate
an error interrupt if EIEN is enabled.
“0” The error interrupt is disabled and no error
“1” The error interrupt is enabled and a
Buffer Interrupt Enable. The IEN[14:0] allow
the user to enable/disable interrupt source for
each of the message buffers i.e., IEN14 config-
ures buffer14 and IEN0 configures buffer0.
“0” buffer as interrupt source disabled
“1” buffer as interrupt source enabled
BM[28:18] RTR
ID[10:0]
interrupt will be generated.
change in REC/TEC will cause an inter-
rupt to be generated.
14
RTR
SRR
r/w
r/w
0
0
1
a
IEN[14:0]
IDE
IDE
IDE
BM[17:0]
ID[17:0]
www.national.com
XRTR
unused
0
XRTR
RTR
0