CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 78

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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19.0 ACCESS.bus Interface
The ACCESS.bus interface module (ACB) is a two wire serial
interface compatible with the ACCESS.bus physical layer. It
permits easy interfacing to a wide range of low-cost memo-
ries and I/O devices, including: EEPROMs, SRAMs, timers,
A/D converters, D/A converters, clock chips and peripheral
drivers. It is also compatible with Intel’s SMBus and Philips’
I
slave, and can maintain bi-directional communications with
both multiple master and slave devices.
This section presents an overview of the bus protocol, and its
implementation by the module.
19.1
The ACCESS.bus protocol uses a two-wire interface for bi-
directional communications between the ICs connected to
the bus. The two interface lines are the Serial Data Line
(SDA), and the Serial Clock Line (SCL). These lines should
be connected to a positive supply, via a pull-up resistor, and
remain HIGH even when the bus is idle.
The ACCESS.bus protocol supports multiple master and
slave transmitters and receivers. Each IC has a unique ad-
dress and can operate as a transmitter or a receiver (though
some peripherals are only receivers).
During data transactions, the master device initiates the
transaction, generates the clock signal and terminates the
transaction. For example, when the ACB initiates a data
transaction with an attached ACCESS.bus compliant periph-
eral, the ACB becomes the master. When the peripheral re-
sponds and transmits data to the ACB, their master/slave
(data transaction initiator and clock generator) relationship is
unchanged, even though their transmitter/receiver functions
are reversed.
19.1.1
One data bit is transferred during each clock pulse. Data is
sampled during the high state of the serial clock (SCL). Con-
sequently, throughout the clock’s high period, the data should
remain stable (see Figure 39). Any changes on the SDA line
during the high state of the SCL and in the middle of a trans-
action aborts the current transaction. New data should be
sent during the low SCL state. This protocol permits a single
data line to transfer both command/control information and
data using the synchronous serial clock.
2
C bus. The module can be configured as a bus master or
— ACCESS.bus, SMBus and I
— ACCESS.bus master and slave
— Supports polling and interrupt controlled operation
— Generate a wake-up signal on detection of a Start Con-
— Optional internal pull-up on SDA and SCL pins
dition, while in power-down mode
Data Transactions
ACB PROTOCOL OVERVIEW
2
C compliant
78
Each data transaction is composed of a Start Condition, a
number of byte transfers (set by the software), and a Stop
Condition to terminate the transaction. Each byte is trans-
ferred with the most significant bit first, and after each byte (8
bits), an Acknowledge signal must follow.
At each clock cycle, the slave can stall the master while it
handles the previous data, or prepares new data. This can be
done for each bit transferred or on a byte boundary by the
slave holding SCL low to extend the clock-low period. Typi-
cally, slaves extend the first clock cycle of a transfer if a byte
read has not yet been stored, or if the next byte to be trans-
mitted is not yet ready. Some microcontrollers with limited
hardware support for ACESS.bus extend the access after
each bit, thus allowing the software time to handle this bit.
Start and Stop
The ACCESS.bus master generates Start and Stop Condi-
tions (control codes). After a Start Condition is generated the
bus is considered busy and it retains this status until a certain
time after a Stop Condition is generated. A high-to-low tran-
sition of the data line (SDA) while the clock (SCL) is high in-
dicates a Start Condition. A low-to-high transition of the SDA
line while the SCL is high indicates a Stop Condition
(Figure40).
In addition to the first Start Condition, a repeated Start Con-
dition can be generated in the middle of a transaction. This
allows another device to be accessed, or a change in the di-
rection of the data transfer.
Acknowledge Cycle
The Acknowledge Cycle consists of two signals: the ac-
knowledge clock pulse the master sends with each byte
SDA
SCL
SCL
SDA
Figure 40.
Start
Condition
S
Figure 39. Bit Transfer
Data Line
Stable:
Data Valid
Start and Stop Conditions
Change
of Data
Allowed
Stop
Condition
P