CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 25

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.1.11
The FLERASE register is a byte-wide read/write register that
controls the erase pulse width. This value is loaded into the
upper 8 bits of the flash timing counter, and at the same time,
11
erase the program memory for the first time, program the
FLERASE register with the proper prescaler value, FTER.
The flash timing counter generates a erase pulse width of
4 (FTER + 1) prescaler output clocks. The default value pro-
vides a delay time of 1ms when the prescaler output clock is
200kHz. Do not modify this register while a program or erase
operation is in progress.
Upon reset, this register resets to 31
ory on the chip is in idle state.
For mass erase, this value should be changed to C7
generate a pulse width that is four times as long as the page
erase.
9.1.12
The FLEND register is a byte-wide read/write register that
controls the delay time after a program/erase operation. This
value is loaded into the lower 8 bits of the flash timing
counter, and at the same time, 00
bits. Before you program or erase the program memory for
the first time, program the FLEND register with the proper
prescaler value, FTEND. The flash timing counter generates
a delay of (FTEND + 1) prescaler output clocks. The default
value provides a delay time of 5 s when the prescaler output
clock is 200kHz. Do not modify this register while program/
erase operation is in progress.
Upon reset, this register resets to 00
ory on the chip is in idle state.
For mass erase, this value should be changed to 13
vide for a delay time twenty times that of the standard delay.
9.1.13
The FLPCNT register is a byte-wide read-only register that
returns the value of the program memory prescaler counter.
FPCNT contains the flash timing prescaler present count val-
ue.
9.1.14
The FLCNT1 register is a byte-wide read-only register that
returns the lower 8 bits of the program memory timing
counter value. FLCNTL is the lower 8 bits of the flash timer
present count value.
9.1.15
The FLCNT2 register is a byte-wide read-only register that
returns the upper 2 bits of the program memory timing
counter value and also the state of the key flash memory in-
terface timing signals. The interface timing signals are only
used in special test modes. Their function is beyond the
scope of this document.
2
is loaded into the lower 2 bits. Before you program or
Program Memory Erase Time Reload Register
(FLERASE)
Program Memory End Time Reload Register
(FLEND)
Program Memory Prescaler Count Register
(FLPCNT)
Program Memory Timer Count Register 1
(FLCNT1)
Program Memory Timer Count Register 2
(FLCNT2)
2
is loaded into the upper 2
1 6
16
when the flash mem-
when the flash mem-
16
to pro-
16
to
25
9.1.16
The PGMKEY register is a byte-wide, write-only register that
must be written with a key value (A3
each write to the flash EEPROM program memory. Other-
wise, the write operation to the program memory will fail. This
feature is intended to prevent unintentional programming of
the program memory.
Reading this register always returns FF hex.
Upon reset, the write enable status that is generated as a re-
sult of writing to this key register is cleared.
9.2
The static RAM memory is used for temporary storage of
data and for the program and interrupt stacks. The 3K bytes
of this memory reside in the address range of C000-CBFF
hex. Each memory access requires one clock cycle, for a
byte or word access. No wait cycles or hold cycles are re-
quired. For non-aligned word access, each memory access
requires multiple clock cycles.
9.3
The flash EEPROM data memory is used for non-volatile
storage of data. The 2K bytes of low endurance memory re-
side in the address range of E800-EFFF hex and the 128
bytes of high endurance memory reside in the address range
of F000-F07F hex. The CPU reads or writes this memory by
using ordinary byte-wide or word-wide memory access com-
mands. This memory shares the same array as the ISP flash
program memory.
This memory also support flash memory test mode and there
is no read protection or permanent write protection for this
memory.
9.3.1
The flash EEPROM data memory read accesses can oper-
ate without wait cycles with a CPU clock rate of up to 20MHz
in the normal mode. At higher clock rates, read accesses can
operate with one wait state.
The programmed number of wait cycles used (either zero or
one) is controlled by a bit in the Data Memory Control Status
register (DMCSR.ZEROWS). This register is described in
Section9.3.3.
9.3.2
Before you begin programming the flash EEPROM data
memory, you should set the value in the EEPROM Data
Memory Prescaler register. This register sets the prescaler
used to generate the data memory programming clock from
the system clock, as described in Section9.3.4.
A code fetch from ISP flash EEPROM program memory is
not possible while flash EEPROM data memory is being pro-
grammed because they share the same memory array.
After the CPU performs a write to the flash EEPROM data
memory, the on-chip hardware completes the EEPROM pro-
gramming in the background. When programming begins,
the on-chip hardware sets the DMCSR.DMBUSY bit to 1,
and also sets the MSTAT.PGMBUSY bit to 1. When program-
ming is completed, it resets these status bits back to 0. Once
the software writes to the flash EEPROM data memory, it
should not attempt to access the EEPROM data memory
Program Memory Write Key Register (PGMKEY)
Reading
Programming
RAM MEMORY
FLASH EEPROM DATA MEMORY
16
) immediately prior to
www.national.com