IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 36

• Manufacturer Part Number: IPR-RLDRAMII
• Description: IP CORE Renewal Of IP-RLDRAMII
• Manufacturer: Altera
• Series: Memory Controllers - SDRAMr
• Type: MegaCorer

Specifications of IPR-RLDRAMII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Tool Function: Intellectual Property (IP) Core
• Supported Devices: HardCopy, Stratix
• Function: RLDRAM II Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
2–26
RLDRAM II Controller MegaCore Function User Guide
local_wdata[]
local_write_req
local_init_done
local_rdata[]
local_rdata_valid
[]
local_wdata_req
rldramii_dq[]
rldramii_qk[]
rldramii_q[]
Table 2–4. Local Interface Signals (Part 2 of 2)
Table 2–5. Memory Interface Signals (Part 1 of 2)
Name
Name
Data-bus width
1 to 9
Data-bus width
Data-bus width × 2
1
1
Data-bus width × 2
The number of
RLDRAM II devices
attached to memory
interface
1
Table 2–5
Width
(Bits)
Width
(Bits)
shows the memory interface signals.
MegaCore Version 9.1
Bidirectional Memory data bus. CIO devices only.
Bidirectional In DQS mode, the memory data strobe signal
Input
Direction
Input
Output
Input
Output
Output
Output
Direction
Write data bus. The local interface must request
local_wdata[]
construct the write data for any requested write
bursts. If the memory burst length is set to two
beats, the write data is requested in a single
clock cycle at the local interface.
Write request signal.
Memory initialization complete signal which is
asserted when the controller has completed its
initialization of the memory. Reads and writes
should not be requested until
local_init_done
Read data bus. The controller returns
local_rdata[]
any requested read transactions. If the memory
burst length is set to two beats, the read data is
returned in a single clock cycle at the local
interface.
Read data valid signal, which indicates that valid
data is present on the read data bus. The
local_rdata_valid[]
the local read data,
only one
attached RLDRAM II device.
Write data request signal. When the local
interface asserts
write data for the burst should be available in
contiguous clock cycles.
that captures read data into the Altera device; in
non-DQS mode, the RLDRAM II controller does
not use
Memory read data bus. SIO devices only.
rldramii_qk[]
local_rdata_valid[]
local_wdata_req
Description
Description
over multiple clock cycles to
over multiple clock cycles for
local_rdata[]
is asserted.
.
signal is aligned with
Altera Corporation
November 2009
per
. There is
, all the