IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 7

• Manufacturer Part Number: IPR-RLDRAMII
• Description: IP CORE Renewal Of IP-RLDRAMII
• Manufacturer: Altera
• Series: Memory Controllers - SDRAMr
• Type: MegaCorer

Specifications of IPR-RLDRAMII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Tool Function: Intellectual Property (IP) Core
• Supported Devices: HardCopy, Stratix
• Function: RLDRAM II Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 1–1. RLDRAM II Controller System-Level Diagram
Note to
(1)
Altera Corporation
November 2009
Non-DQS mode only.
Figure
or Fail
Clock
Pass
1–1:
Example Design
Example
Fedback
System
PLL ( 1 )
Driver
Clock
DLL
PLL
IP Toolbench generates the following items:
■
■
A testbench, which instantiates the example design
A synthesizable example design which instantiates the following
modules:
●
●
●
●
Interface
Local
RLDRAM II controller:
•
•
Example driver—generates write, read and refresh requests and
outputs a pass_fail signal to indicate that the tests are
passing or failing
System phase-locked loop (PLL)—generates the RLDRAM II
controller clocks
Delay locked loop (DLL)—instantiated in DQS mode and
generates the DQS delay control signal for the dedicated DQS
delay circuitry
MegaCore Version 9.1
Encrypted control logic, which takes transaction requests
from the local interface and issues writes, reads, and
refreshes to the memory interface
A clear-text datapath
RLDRAM II Controller
RLDRAM II Controller MegaCore Function User Guide
Control Logic
(Encrypted)
(Clear Text)
Datapath
RLDRAM II
About This MegaCore Function
Interface
RLDRAM II
1–3