IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 38

• Manufacturer Part Number: IPR-RLDRAMII
• Description: IP CORE Renewal Of IP-RLDRAMII
• Manufacturer: Altera
• Series: Memory Controllers - SDRAMr
• Type: MegaCorer

Specifications of IPR-RLDRAMII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Tool Function: Intellectual Property (IP) Core
• Supported Devices: HardCopy, Stratix
• Function: RLDRAM II Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Parameters
Parameters
2–28
RLDRAM II Controller MegaCore Function User Guide
control_a[]
control_ba[]
control_cs_n
control_dm[]
control_doing_wr
control_ref_n
control_wdata[]
control_wdata_
valid
control_we_n
control_qvld[]
control_rdata[]
Table 2–6. Datapath Interface Signals
Name
local_addr[]
3
1
The number of
RLDRAM II devices
attached to the
memory interface ×
2
1
1
Data-bus width × 2
1
1
The number of
RLDRAM II devices
attached to the
memory interface
Data-bus width × 2
Table 2–6
The parameters can only be set in IP Toolbench (see
Parameterize” on page
Width
(Bits)
shows the datapath interface signals.
MegaCore Version 9.1
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Direction
3–5).
Address bits.
Bank address bits.
Chip select signal.
The DM bus, which has valid data in the same clock
cycles that
Control_doing_wr
controller is writing to the RLDRAM II devices and
controls the output enables on
rldramii_d[]
Refresh signal.
The write data bus, which has valid data in the same
clock cycles that
asserted.
Enables the write data bus and DM enable registers
so that they are only updated when valid data and
enables are available.
Write enable signal.
The read data valid flag.There is only one QVLD flag
per RLDRAM II device. The
signal is aligned with the valid
and is asserted during this period. The
control_qvld[]
functionality as
The captured read data (same as
local_rdata[]
control_wdata_valid
local_rdata_valid[]
control_wdata_valid
.
).
Description
signal has the same
is asserted when the
control_qvld[]
control_rdata[]
“Step 1:
rldramii_dq[]
Altera Corporation
November 2009
is asserted.
.
is
or