IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 26

• Manufacturer Part Number: IPR-RLDRAMII
• Description: IP CORE Renewal Of IP-RLDRAMII
• Manufacturer: Altera
• Series: Memory Controllers - SDRAMr
• Type: MegaCorer

Specifications of IPR-RLDRAMII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Tool Function: Intellectual Property (IP) Core
• Supported Devices: HardCopy, Stratix
• Function: RLDRAM II Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Interfaces
Interfaces
2–16
RLDRAM II Controller MegaCore Function User Guide
f
For more details on how to run the simulation script, see
Example Design” on page
Constraints
The constraints scripts set the following constraints:
■
■
■
■
■
■
■
■
This section describes the following RLDRAM II commands:
■
■
■
■
Initialization
The control logic initializes the RLDRAM II devices. During initialization
the mode register is set and each bank is refreshed in turn. IP Toolbench
sets the following RLDRAM II initialization features:
■
■
■
■
Figure 2–11
Sets IO standards:
●
●
●
●
Sets output capacitance
Places data pins as per selection in pin placement constraints floor
plan. Allows automatic placement for DQS and non-DQS modes
Places all DM pins
Sets up correct output enable groups
Sets rldramii_a_0, rldramii_ba_0, rldramii_cs_n_0,
rldramii_ref_n_0 and rldrainii_we_n_0 as fast output
registers (see note
Sets rldramii_qk[] non-global signal in DQS capture mode
Add Hold Relationship and Setup Relationship to all I/O ports.
Initialization
Writes
Reads
Refreshes
On-die termination (ODT)
Impedance matching resistor
DLL enable
RLDRAM II configuration
1.5 or 1.8-V HSTL voltage selection
Address and command—HSTL Class I
Data CIO mode—HSTL Class II
Data SIO mode—HSTL Class I
shows the initialization sequence.
MegaCore Version 9.1
1
in
3–11.
Table
2–5)
Altera Corporation
“Simulate the
November 2009