IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 53

• Manufacturer Part Number: IPR-RLDRAMII
• Description: IP CORE Renewal Of IP-RLDRAMII
• Manufacturer: Altera
• Series: Memory Controllers - SDRAMr
• Type: MegaCorer

Specifications of IPR-RLDRAMII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Tool Function: Intellectual Property (IP) Core
• Supported Devices: HardCopy, Stratix
• Function: RLDRAM II Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
November 2009
<variation name>.vhd, or .v
<variation name>.cmp
<variation name>.bsf
<variation name>.sdc
altera_vhdl_support.vhd
<variation name>_example_driver.vhd or .v
<top-level name>.vhd or .v
add_constraints_for_<variation name>.tcl
rldramii_pll_<device name>.vhd or .v
rldramii_fbpll_<device name>.vhd or .v
<variation
name>_auk_rldramii_addr_cmd_reg.vhd or .v
<variation name>_auk_rldramii_clk_gen.vhd or .v
<variation
name>_auk_rldramii_controller_ipfs_wrapper.vh
d or .v
<variation
name>_auk_rldramii_controller_ipfs_wrapper.vh
o or .vo
<variation name>_auk_rldramii_datapath.vhd or .v Datapath.
Table 3–1. Generated Files (Part 1 of 2)
Filename
Table 3–1
project directory. The names and types of files specified in the IP
Toolbench report vary based on whether you created your design with
VHDL or Verilog HDL
describes the generated files and other files that may be in your
MegaCore Version 9.1
Note
(1), (2),
RLDRAM II Controller MegaCore Function User Guide
A MegaCore function variation file, which defines a
VHDL or Verilog HDL description of the custom
MegaCore function. Instantiate the entity defined by this
file inside of your design. Include this file when compiling
your design in the Quartus II software.
A VHDL component declaration file for the MegaCore
function variation. Add the contents of this file to any
VHDL architecture that instantiates the MegaCore
function.
Quartus II symbol file for the MegaCore function
variation. You can use this file in the Quartus II block
diagram editor.
A Synopsys Design Constraints (SDC) file. Use this SDC
file with the DDR timing wizard (DTW)-generated SDC
file when using TimeQuest. You must copy the contents
of this file into the DTW-generated SDC file, so the
example design has the correct timing constraints when
using TimeQuest.
A VHDL package that contains functions for the
generated entities. This file may be shared between
MegaCore functions.
Example driver.
Example design file.
Add constraints script.
System PLL.
Fedback PLL.
Address and command output registers.
Memory clock generator.
A file that instantiates the controller.
VHDL or Verilog HDL IP functional simulation model.
(3)
Description
Getting Started
3–9