IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 30

• Manufacturer Part Number: IPR-RLDRAMII
• Description: IP CORE Renewal Of IP-RLDRAMII
• Manufacturer: Altera
• Series: Memory Controllers - SDRAMr
• Type: MegaCorer

Specifications of IPR-RLDRAMII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Tool Function: Intellectual Property (IP) Core
• Supported Devices: HardCopy, Stratix
• Function: RLDRAM II Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Interfaces
Figure 2–14. Read Example
2–20
RLDRAM II Controller MegaCore Function User Guide
RLDRAM II Interface
local_rdata_valid[]
local_bank_addr[]
local_write_req
Local Interface
local_read_req
rldramii_clk_n
rldramii_we_n
rldramii_qvld[]
rldramii_ref_n
rldramii_cs_n
rldramii_dm[ ]
f
local_rdata[]
rldramii_ba[]
rldramii_qk[]
local_addr[]
rldramii_clk
rldramii_a[]
rldramii_d[]
rldramii_q[]
clk
During reads, the local interface indicates that read data is valid by
asserting the local_rdata_valid[] signal. All captured read data is
clocked off the clock that captures the RLDRAM II read data. In DQS
mode, this clock is the delayed DQS signal, capture_clk[], sourced
from the dedicated DQS delay circuitry. In non-DQS mode this clock is
the external capture clock, non_dqs_capture_clk.
Figure 2–14
In this example, the memory burst length is set to eight beats. The
RLDRAM II device is setup with a t
two).
Figure 2–15
RLDRAM II interface. In this example, the memory burst length is set to
eight beats. The RLDRAM II device is setup with a t
(configuration two).
For more information about bus turnaround timing calculations with
CIO devices, refer to AN 325: Interfacing RLDRAM II with Stratix II,
Stratix & Stratix GX Devices.
A
A
shows an example of a read at an SIO RLDRAM II interface.
shows an example of a read following a write at a CIO
A
MegaCore Version 9.1
A
B
B
B
B
B
B
C C
C C
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 7
11
A01 A23 A45 A67 B01 B23 B45 B67 C01 C23C45 C67
RC
of six-clock cycles (configuration
C
C
RC
of six-clock cycles
Altera Corporation
November 2009
C67