IPR-RLDRAMII Altera, IPR-RLDRAMII Datasheet - Page 41

• Manufacturer Part Number: IPR-RLDRAMII
• Description: IP CORE Renewal Of IP-RLDRAMII
• Manufacturer: Altera
• Series: Memory Controllers - SDRAMr
• Type: MegaCorer

Specifications of IPR-RLDRAMII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Tool Function: Intellectual Property (IP) Core
• Supported Devices: HardCopy, Stratix
• Function: RLDRAM II Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
November 2009
Number of address
and command and
write data pipeline
registers
Number of read data
pipeline registers
Address and
command clock
Address and
command clock edge
Dedicated address
and command clock
PLL phase offset
Enable DQS mode
Use migratable byte
groups
Fedback PLL phase
offset
Table 2–10. Pipeline Options
Table 2–11. Clocking Modes
Parameter
Parameter
0, 1, 2 or 3
0, 1, 2 or 3
System, write,
or dedicated
Falling or rising
± 180
On or off
On or off
± 180
Range
Range
Timing
Table 2–10
Table 2–11
When you choose 1, 2, or 3 the wizard inserts 1, 2, or 3 pipeline
registers between the memory controller and the command and
address output registers and the write data output registers. These
registers may help to achieve the required performance at higher
frequencies.
When you choose 1, 2, or 3 the wizard inserts 1, 2, or 3 pipeline
registers between the read capture registers and the memory
controller. These registers may help to achieve the required
performance at higher frequencies.
The clock for the address and command output registers. For
system_clk
for a separate clock, choose Dedicated.
If you choose Dedicated for the clock, ensure the clock phase allows
the Quartus II software to meet the setup time on the address and
command output registers.
The clock edge on which the addresses and commands are output.
Sets the dedicated address and command clock PLL phase for better
timing.
Turn on for DQS mode; otherwise the controller is in non-DQS mode
(Stratix II and Stratix II GX devices only). HardCopy II devices allow
DQS mode only.
When turned on, you can migrate the design to a migration device.
When turned off the wizard allows much greater flexibility in the
placement of byte groups. You can only turn on this option when
Enable DQS mode is turned off.
Sets the fedback clock PLL phase for read capture (non-DQS mode
only).
shows the clocking modes.
shows the pipeline options.
MegaCore Version 9.1
RLDRAM II Controller MegaCore Function User Guide
choose System; for
Description
Description
write_clk
Functional Description
, choose Write, and
2–31