IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 20

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

QDRII SRAM Controller Walkthrough
2–10
QDRII SRAM Controller MegaCore Function User Guide
Notes to
(1)
(2)
(3)
<variation
name>_auk_qdrii_sram_pipe_resynch_wrapper.v
hd or .v
<variation
name>_auk_qdrii_sram_pipeline_addr_cmd.vhd
or .v
<variation
name>_auk_qdrii_sram_pipeline_rdata.vhd or .v
<variation
name>_auk_qdrii_sram_pipeline_wdata.vhd or .v
<variation
name>_auk_qdrii_sram_read_group.vhd or .v
<variation
name>_auk_qdrii_sram_resynch_reg.vhd or .v
<variation
name>_auk_qdrii_sram_train_wrapper.vhd or .v
<variation
name>_auk_qdrii_sram_test_group.vhd or .v
<variation
name>_auk_qdrii_sram_write_group.vhd or .v
<variation name>.qip
<top-level name>.vhd or .v
add_constraints_for_<variation name>.tcl
qdrii_pll_stratixii.vhd or .v
Table 2–1. Generated Files (Part 2 of 2) (1),
<top-level name> is the name of the Quartus II project top-level entity.
<variation name> is the name you give to the controller you create with the Megawizard.
IP Tooblench replaces the string qdrii_sram with qdriiplus_sram for QDRII+ SRAM controllers.
Table
2–1:
Filename
(1)
2.
You have finished the walkthrough. Now, simulate the example design
(refer to
(refer to
Example Design” on page
After you review the generation report, click Exit to close IP
Toolbench.
“Edit the PLL” on page
“Simulate the Example Design” on page
MegaCore Version 9.1
(2)
&
File that includes the write data pipeline and includes the
address and command, read command, write data, and
write command pipeline.
Address and command pipeline.
Read data pipeline.
Write data pipeline.
The read registers.
The resynchronization FIFO buffers.
File that contains all the training group modules.
Training module, which realigns latency.
The write registers.
Contains Quartus II project information for your
MegaCore function variations.
Example design file.
The add constraints script.
Stratix II PLL.
(3)
2–19).
2–18), and compile (refer to
Description
2–11), edit the PLL(s)
Altera Corporation
November 2009
“Compile the