IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 35

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3–3. Resynchronization & Pipeline Logic Block Diagram
Altera Corporation
November 2009
Read FSM
To Control
Control
Control
Block
Logic
Logic
From
From
Read Data
Optional
Pipeline
Address &
Command
Write Data
Resynchronization & Pipeline Logic
Figure 3–3
diagram.
Optional
Address & Command Pipeline
The optional address and command pipeline pipelines all commands and
addresses by a predefined number of cycles.
Pipeline
Optional
Pipeline
shows the resynchronization and pipeline logic block
MegaCore Version 9.1
Resynchronization
Resynchronization
& Pipeline Logic
Training
Module
Group
QDRII SRAM Controller MegaCore Function User Guide
Training Group
Modules
Resynchronization
Training
Module
Group
Functional Description
From Datapath
Capture
Registers
3–3