IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 54

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Interfaces & Signals
Figure 3–19. Simultaneous Read & Write—Burst of Four (Wide Mode)
3–22
QDRII SRAM Controller MegaCore Function User Guide
avl_wait_request_wr
avl_wait_request_rd
avl_data_read_valid
avl_data_wr[17:0]
avl_data_rd[17:0]
avl_adr_wr[19:0]
avl_adr_rd[19:0]
qdrii_a[19:0]
qdrii_d[17:0]
qdrii_q[17:0]
qdrii_wpsn
qdrii_rpsn
qdrii_cqn
avl_read
avl_write
qdrii_cq
avl_clk
qdrii_k
1234 5678
51
01
Signals
Table 3–1
avl_clk
avl_clk_wr
avl_resetn
dll_delay_ctrl[6]
Table 3–1. System Signals (Part 1 of 2)
5678
02
02
52
52
Signal
shows the system signals.
MegaCore Version 9.1
1 2 3 4 5 6 7 8 8
51
01
52
Input
Input
Input
Input
Direction
02
02
9 a b c d e f 0 0
System clock derived from the PLL.
Write clock derived from the PLL.
Reset signal, which you can assert
asynchronously, but you must
deassert synchronously to
Delay bus for DLL to shift DQS inputs.
DQS mode only.
Description
9abc
Altera Corporation
November 2009
avl_clk
dfe0
dfe0
.