IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 21

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Simulate the
Example Design
Altera Corporation
November 2009
f
This section describes the following simulation techniques:
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Simulate with IP Functional Simulation Models
You can simulate the example design using the IP Toolbench-generated IP
functional simulation models. IP Toolbench generates a VHDL or Verilog
HDL testbench for your example design, which is in the testbench
directory in your project directory.
For more information on the testbench, refer to
page
You can use the IP functional simulation model with any
Altera-supported VHDL or Verilog HDL simulator. The instructions for
the ModelSim simulator are different to other simulators.
Simulating With the ModelSim Simulator
Altera supplies a generic memory model, lib\qdrii_model.v, which
allows you to simulate the example design with the ModelSim simulator.
To simulate the example design with the ModelSim
these steps:
1.
2.
3.
4.
5.
Simulate with IP Functional Simulation Models
Simulating With the ModelSim Simulator
Simulating With Other Simulators
Simulating in Third-Party Simulation Tools Using NativeLink
Copy the generic memory model to the <directory name>\testbench
directory.
Open the memory model and the testbench (<top-level
name>_vsim.v or .vhd) in a text editor and ensure the signal names
have the same capitalization in both files.
Start the ModelSim-Altera simulator.
Change your working directory to your IP Toolbench-generated file
directory <directory name>\testbench\modelsim.
To simulate with an IP functional simulation model simulation, type
the following command:
source <variation name>_vsim.tcl
3–27.
MegaCore Version 9.1
QDRII SRAM Controller MegaCore Function User Guide
r
“Example Design” on
®
simulator, follow
Getting Started
2–11