IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 48

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Interfaces & Signals
Figure 3–12. Isolated Read—Burst of Four (Narrow Mode)
Figure 3–13. Isolated Read—Burst of Two (Wide Mode)
3–16
QDRII SRAM Controller MegaCore Function User Guide
avl_wait_request_rd
avl_data_read_valid
avl_wait_request_rd
avl_data_read_valid
avl_data_rd[19:0]
avl_data_rd[17:0]
avl_data_rd[19:0]
avl_data_rd[17:0]
qdrii_a[19:0]
qdrii_q[17:0]
qdrii_a[19:0]
qdrii_q[17:0]
qdrii_rpsn
qdrii_rpsn
qdrii_cqn
qdrii_cqn
avl_read
avl_read
qdrii_cq
qdrii_cq
avl_clk
avl_clk
qdrii_k
qdrii_k
0001
0001
0001
0001
Figure 3–13
burst of two. The principle is identical to the burst of four, but all the data
bits coming back are transferred onto the Avalon interface. The timing on
the QDRII SRAM interface is slightly different as the address is only
present for half a clock cycle.
shows a single read request from the Avalon interface for a
MegaCore Version 9.1
0001
0001
0001
0001
01 02 xx
01 02
02
xx xx
Altera Corporation
November 2009
0102
0102
0102
0102