PAC-POWR607-EV Lattice, PAC-POWR607-EV Datasheet - Page 10

• Manufacturer Part Number: PAC-POWR607-EV
• Description: MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of PAC-POWR607-EV

• Processor To Be Evaluated: ispPAC-POWR607
• Interface Type: JTAG
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.96 V
• Core Architecture: CPLD
• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR607
• Primary Attributes: -
• Secondary Attributes: 4.5 ~ 9 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 4-6. Verify Timing Diagram
Figure 4-7. Discharge Timing Diagram
Theory of Operation
Analog Monitor Inputs
The ispPAC-POWR607 provides six independently programmable voltage monitor input circuits as shown in
Figure 4-8. One programmable trip-point comparator is connected to each analog monitoring input. Each compara-
tor reference has 192 programmable trip points over the range of 0.667V to 5.811V. Additionally, a 75mV ‘zero-
detect’ threshold is selectable which allows the voltage monitors to determine if a monitored signal has dropped to
ground level. This feature is especially useful for determining if a power supply’s output has decayed to a substan-
tially inactive condition after it has been switched off.
Figure 4-8. ispPAC-POWR607 Voltage Monitors
Figure 4-8 shows the functional block diagram of one of the six voltage monitor inputs - ‘x’ (where x = 1...6). Each
voltage monitor can be divided into two sections: Analog Input, and Filtering.
The voltage input is monitored by a programmable trip-point comparator. Table 4-1 and Table 4-2 show all trip
points and ranges to which any comparator’s threshold can be set.
State
TCK
TMS
State
TCK
TMS
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIL
Update-IR
Update-IR
t
SU1
t
SU1
VMONx
t
CKH
t
H
Run-Test/Idle (Erase or Program)
t
CKH
t
SU1
t
t
H
CKL
t
SU1
t
CKL
Run-Test/Idle (Program)
t
H
Analog
ispPAC-POWR607
Input
Trip Point
t
H
t
PWP
t
SU1
t
PWV
t
Select-DR Scan
CKH
t
SU1
t
H
4-10
Select-DR Scan
t
CKH
t
H
Glitch
Filter
t
SU1
t
HVDIS
Signal
Logic
(Actual)
ispPAC-POWR607 Data Sheet
t
CKH
t
H
t
t
Run-Test/Idle (Verify)
SU1
SU1
t
CKL
Array
PLD
t
CKH
Specified by the Data Sheet
t
CKH
t
H
Update-IR
t
H
t
PWV
t
SU1
t
CKL
t
Actual
SU1
t
PWV
t
CKH
t
H
t
CKH
t
H