PAC-POWR607-EV Lattice, PAC-POWR607-EV Datasheet - Page 9

• Manufacturer Part Number: PAC-POWR607-EV
• Description: MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of PAC-POWR607-EV

• Processor To Be Evaluated: ispPAC-POWR607
• Interface Type: JTAG
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.96 V
• Core Architecture: CPLD
• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR607
• Primary Attributes: -
• Secondary Attributes: 4.5 ~ 9 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Timing for JTAG Operations
Figure 4-4. Erase (User Erase or Erase All) Timing Diagram
Figure 4-5. Programming Timing Diagram
t
t
t
t
t
t
t
t
t
t
f
t
t
t
ISPEN
ISPDIS
HVDIS
HVDIS
CEN
CDIS
SU1
H
CKH
CKL
MAX
CO
PWV
PWP
Symbol
TMS
TCK
State
State
TCK
TMS
VIH
VIH
VIL
VIL
Program enable delay time
Program disable delay time
High voltage discharge time, program
High voltage discharge time, erase
Falling edge of TCK to TDO active
Falling edge of TCK to TDO disable
Setup time
Hold time
TCK clock pulse width, high
TCK clock pulse width, low
Maximum TCK clock frequency
Falling edge of TCK to valid output
Verify pulse width
Programming pulse width
VIH
VIH
VIL
VIL
Update-IR
Update-IR
t
SU1
t
SU1
t
CKH
t
H
Parameter
t
CKH
t
SU1
t
t
GKL
H
Run-Test/Idle (Erase)
t
SU1
t
CKL
Run-Test/Idle (Program)
t
H
t
H
t
SU1
t
PWP
Select-DR Scan
t
CKH
t
t
H
SU1
Conditions
4-9
t
Select-DR Scan
CKH
t
H
t
SU1
Min.
200
10
30
30
10
20
20
30
20
—
—
—
—
5
t
CKH
t
H
ispPAC-POWR607 Data Sheet
t
Run-Test/Idle (Discharge)
SU1
t
SU1
t
GKL
Typ.
t
Specified by the Data Sheet
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CKH
t
t
H
CKH
Update-IR
t
H
t
SU2
t
SU1
t
CKL
t
SU1
Max.
10
10
25
10
—
—
—
—
—
—
—
—
—
—
t
CKH
t
t
CKH
H
t
H
Units
MHz
ms
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns