PAC-POWR607-EV Lattice, PAC-POWR607-EV Datasheet - Page 17

• Manufacturer Part Number: PAC-POWR607-EV
• Description: MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of PAC-POWR607-EV

• Processor To Be Evaluated: ispPAC-POWR607
• Interface Type: JTAG
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.96 V
• Core Architecture: CPLD
• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR607
• Primary Attributes: -
• Secondary Attributes: 4.5 ~ 9 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
logic signals, LEDs, opto-couplers, and power supply control inputs. The HVOUT[1:2] pins can also be configured
as high voltage FET drivers and are discussed more in the next section. The digital I/O pins can also be pro-
grammed to be true digital inputs.
It should be noted the IN_OUT[3:7] pins are not true bidirectional pins and individually they can only act as an input
or as an output, but not both at the same time. A simplified diagram of how this is accomplished is shown in
Figure 4-13. There is a user configurable E
the pin is a dedicated input or open drain output.
Figure 4-13. Programmable Digital Input/Output Pins (IN_OUT)
The architecture takes advantage of routing that normally feeds all PLD macrocell outputs back into the input AND
array. Output pins are realized when some number of macrocell outputs are selected from the PLD to become dig-
ital open drain outputs. When programmed to be outputs, IN_OUTx pins are configured exactly this way. When pro-
grammed to be digital input pins, the open drain buffer is permanently turned off (set to Hi-Z) and the input from
IN_OUTx pin goes to the input array instead of the macrocell’s output. The macrocell output is still available and
can be connected to a different output pin if desired. When the IN-OUTx pins are configured as digital input pins,
the signal is registered by MCLK prior to going to the input AND array the same as the IN1 and IN2 digital inputs.
High-Voltage Outputs
The ispPAC-POWR607’s HVOUT1-HVOUT2 output pins can be programmed to operate either as high-voltage FET
drivers or optionally as open drain digital outputs. Figure 4-14 shows the details of the HVOUT gate drivers. Each
of these outputs is controlled from the PLD.
Figure 4-14. Basic Function Diagram for an Output in High Voltage MOSFET Gate Driver Mode
Figure 4-14 shows the HVOUT functionality when programmed as a FET driver. In this mode the output either
sources current from a charge pump or sinks current. The voltage that the output level at the pin will rise to is typi-
cally 9V. (This level is not programmable, unlike other Power Manager II devices). The maximum voltage levels
required depend on the gate-to-source threshold of the FET being driven and the power supply voltage being
switched. The maximum voltage level needs to be sufficient to bias on the gate-to-source threshold and also
Digital Control
from PLD
Charge Pump
to PLD Input
Array
(E
I/O Config
(9V)
macrocell
2
CMOS)
outputs
from
Input / Feedback Mux
+
-
2
CMOS bit for each of the IN_OUT[3:7] pins that determines whether
(1mA, min.)
1
0
2.5mA
I
SINK
Routing
Output
4-17
I
SOURCE
(15 µA)
Open Drain
Output Buffer
Input Buffer
HVOUTx
Pin
ispPAC-POWR607 Data Sheet
IN_OUTx
Supply
Input
Load