PAC-POWR607-EV Lattice, PAC-POWR607-EV Datasheet - Page 16

• Manufacturer Part Number: PAC-POWR607-EV
• Description: MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of PAC-POWR607-EV

• Processor To Be Evaluated: ispPAC-POWR607
• Interface Type: JTAG
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.96 V
• Core Architecture: CPLD
• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR607
• Primary Attributes: -
• Secondary Attributes: 4.5 ~ 9 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Digital Inputs and Optional Device Power Down
The ispPAC-POWR607 has two dedicated digital input pins which are registered by MCLK as shown in Figure 4-10
and then connect to the input AND array of the PLD (IN[1:2]). The pins are standard CMOS inputs and are refer-
enced to VCC.
The optional power-down mode is a programmable feature controlled via the IN1_PWRDN pin. It is used to power-
down the ispPAC-POWR607 and power it up again as desired. When in power-down mode, the ispPAC-POWR607
draws a minimal amount of supply current (less than 10µA max). The device is brought out of power-down mode by
applying a logic high signal on the level sensitive IN1_PWRDN pin.
When it exits power-down mode, the ispPAC-POWR607 is internally reset to its initial power-on state before resum-
ing normal operation. The logic and limited memory needed to “wakeup” on cue are all that remain on during
power-down mode. Other functions and capabilities, such as voltage monitoring, FET drive capability and PLD
logic states are all lost when the ispPAC-POWR607 is in power-down mode. Open drain outputs and MOSFET
driver pins go into Hi-Z mode and all digital inputs, except IN1_PWRDN, stop responding to logic input signals.
There are two E
specific power-down functionality is achieved using PAC-Designer, a software design tool for Lattice programmable
mixed signal devices. Table 4-4 is a truth table detailing the operation of the ispPAC-POWR607 power-down logical
control function.
Table 4-4. PWRDN Truth Table
To use the ispPAC-POWR607's power-down function, the E
device design configuration. Power-down is disabled otherwise (the initial default).
When power is first applied to ispPAC-POWR607, the device checks to see if a power-down condition exists, and
then if it is already present will proceed immediately to the power-down state. During the brief period that the
device is on, it will consume full power but it will proceed directly to power-down mode without executing any state
machine instructions, etc. This time to initially detect the power-down command and then shut down is given in the
power-down specifications section of the datasheet.
In addition to the IN1_PWRDN pin, Table 4-4 shows how an alternate signal from the PLD called PLD_PWRDN
can be used to initiate power-down (not the default). This can be useful when power-down is the last step in a
series of ispPAC-POWR607 PLD controlled states, such as turning off supplies in sequence or acknowledging pro-
cessor signals, etc.
Note: The only way to exit power-down mode, regardless of how it's initiated, is with the IN1_PWRDN pin. Applying
a logic high to IN1_PWRDN will always return the ispPAC-POWR607 to normal operation. Finally, whenever the
ispPAC-POWR607 is in power-down mode, VCCJ is internally pulled to GND to turn off the JTAG I/O pins. It is
important, therefore, that the VCCJ pin be open when power-down mode is initiated. If connected to a power supply
during power-down mode, VCCJ will draw approximately 2.2mA.
Dual Purpose Digital I/O Pins
The ispPAC-POWR607 provides seven possible digital outputs, HVOUT[1:2] and IN_OUT[3:7]. Any number of
these pins can be configured to act as open drain outputs, providing a high degree of flexibility when interfacing to
Note: When in power-down mode, the ispPAC-POWR607 will not respond to logic inputs (except to the IN1_PWRDN
IN1_P P P P W W W W R R R R D D D D N N N N
pin) and all outputs will be high impedance.
Input Pin
2
CMOS bits associated with the ispPAC-POWR607 power-down function. Configuring these bits for
X
1
0
0
Internal Signal
PLD_PWRDN
X
X
X
0
PWRDN Enable
Clear
Set
Set
Set
Bit
4-16
Internal Signal PLD_PWRDN
2
CMOS PWRDN enable bit must be set during initial
PWRDN Source Bit
IN1_PWRDN Pin
X
X
ispPAC-POWR607 Data Sheet
Power Mode
Power-down
Power-down
Normal
Normal