PAC-POWR607-EV Lattice, PAC-POWR607-EV Datasheet - Page 28

• Manufacturer Part Number: PAC-POWR607-EV
• Description: MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of PAC-POWR607-EV

• Processor To Be Evaluated: ispPAC-POWR607
• Interface Type: JTAG
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.96 V
• Core Architecture: CPLD
• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR607
• Primary Attributes: -
• Secondary Attributes: 4.5 ~ 9 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Package Options
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet:
Revision History
September 2006
December 2007
December 2008
February 2009
August 2007
June 2008
April 2007
Date
[phone] (Outside North America)
[e-mail]
www.latticesemi.com
Version
01.0
01.1
01.2
01.3
01.4
01.5
01.6
VMON1
VMON2
VMON3
VMON4
VMON5
VCC
NC
NC
Initial release.
References to Die Pad added to Pin Descriptions table, Recommended Operating Condi-
tions table and Package Options diagram.
Changes to HVOUT pin specifications.
Final data sheet.
Added timing diagram and timing parameters to "Power-On Reset" specifications.
Modified PLD Architecture figure to show input registers.
Added 32-pin QFNS package Ordering Part Number information per PCN #13A-08.
Updated ispPAC-POWR607 PLD Architecture diagram to clarify that the digital inputs are
registered inputs to the AND array.
Updated Digital Inputs and Optional Device Power Down text section.
Updated Dual Purpose Digital I/O Pins text section.
1
2
3
4
5
6
7
8
32
9
31
10
ispPAC-POWR607
30
11
32-Pin QFNS
29
12
Die Pad
4-28
NC
28
13
27
14
Change Summary
26
15
25
16
ispPAC-POWR607 Data Sheet
24
23
22
21
20
19
18
17
NC
IN_OUT5
IN_OUT6
VCC
IN_OUT7
TMS
TDI
NC