5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 10

• Manufacturer Part Number: 5M2210ZF256C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M2210ZF256C5N

• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 271
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 201.1MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of Gates: -
• Number Of I /o: 203
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Devices
Stratix IV GX FPGA Features
1
2
3
8
Maximum LVDS channels, transceiver channels, PLLs/unique outputs, and PCIe
This is the base core logic register count. The ALM can support three registers when used
EP4SGX360N has 1,024 18x18 multipliers.
hard IP blocks for the product line shown.Various packages offer a variety of options to
meet your design needs.
in LUTREG mode, which increases the total register count by an additional 50 percent.
ALMs
Equivalent LEs
Registers
M9K memory blocks
M144K memory blocks
MLAB memory (Kb)
Embedded memory (Kb)
18-bit x 18-bit multipliers
Speed grades
(fastest to slowest)
Global clock networks
Regional clock networks
Periphery clock networks
PLLs/unique outputs
Design security
HardCopy series device support
Configuration file size (Mb)
Others
I/O voltage levels supported (V)
I/O standards supported
Emulated LVDS channels,
1,100 Mbps
LVDS channels, 1,600 Mbps
(receive/transmit)
Embedded DPA circuitry
Series, parallel, and
differential OCT
Transceiver (SERDES) channels
(8.5 Gbps/6.5 Gbps)
PCIe hard IP blocks
Memory devices supported
Altera Product Catalog
2
2
7
•
2011
•
www.altera.com
-2, -2x
EP4SGX70
29,040
72,600
58,080
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15, Differential SSTL-18,
6,462
Differential SSTL-2, Differential HSTL-12, Differential HSTL-15, Differential HSTL-18, SSTL-15 (I and II),
56/56
4/34
16/8
462
908
384
128
3
16
64
56
53
SSTL-18 (I and II), SSTL-2 (I and II), 1.2-V HSTL (I and II), 1.5-V HSTL (I and II), 1.8-V HSTL (I and II)
2
4
, -3, -4 -2, -2x
5
EP4SGX110
105,600
42,240
84,480
1,320
8,244
56/56
4/34
16/8
660
512
128
16
64
56
3
53
2
4
, -3, -4 -2, -2x
5
Plug & Play Signal Integrity, Programmable Power Technology
Stratix IV GX FPGAs (0.9 V), 8.5-Gbps Transceivers
EP4SGX180
DDR3, DDR2, DDR, QDR II, RLDRAM II, SDR
175,750
140,600
70,300
11,430
2,197
88/88
24/12
4
5
6
7
8/68
Support for -2 core and -3 I/O speed-grade. Support for PCIe Gen1 and Gen2 x8.
Selected devices only.
For EP4SGX70D and EP4SGX110D/F devices.
The total transceiver count is the sum of 8.5-Gbps transceivers plus 6.5-Gbps transceivers.
950
920
192
3.3-V compliant, requires a 3-V power supply.
20
64
88
95
3
See supported protocols and data rates on page 69
2
4
, -3, -4 -2, -2x
1.2, 1.5, 1.8, 2.5, 3.3
EP4SGX230
228,000
182,400
91,200
14,283
1,235
2,850
1,288
88/88
24/12
8/68
192
22
16
64
88
95
3
3
3
3
2
4
, -3, -4 -2, -2x
EP4SGX290
6
116,480
291,200
232,960
13,608
3,640
12/96
98/98
32/16
936
832
141
256
36
88
88
3
4
4
, -3, -4 -2, -2x
EP4SGX360
1
141,440
353,600
282,880
18,144
1,040
1,248
4,420
12/96
98/98
32/16
141
256
48
88
88
3
4
4
, -3, -4
3
EP4SGX530
212,480
531,200
424,960
-2, -3, -4
20,736
1,280
6,640
1,024
12/96
98/98
32/16
112
172
256
64
88
3
4