5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 12

• Manufacturer Part Number: 5M2210ZF256C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M2210ZF256C5N

• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 271
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 201.1MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of Gates: -
• Number Of I /o: 203
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Devices
Stratix III L FPGA Features
1
2
10
This is the base core logic register count. The ALM can support three registers when used in LUTREG mode, which increases the total register count by an additional 50 percent.
The size of the MLAB ROM is twice the size of the MLAB RAM.
ALMs
Equivalent LEs
Registers
M9K memory blocks
M144K memory blocks
MLAB memory (Kb)
Embedded memory (Kb)
18-bit x 18-bit multipliers
Speed grades
(fastest to slowest)
Global clock networks
Regional clock networks
Periphery clock networks
PLLs/unique outputs
Design security
Configuration file size (Mb)
HardCopy series device support
Others
I/O voltage levels
supported (V)
I/O standards supported
Emulated LVDS channels,
1,100 Mbps
LVDS channels, 1,600 Mbps
(receive/transmit)
Embedded DPA circuitry
Series, parallel, and
differential OCT
Memory devices supported
Altera Product Catalog
1
2
•
2011
•
www.altera.com
EP3SL50
47,500
19,000
38,000
1,836
56/56
4/34
108
297
216
104
48
22
56
6
SSTL-18 (I and II), SSTL-15 (I and II), SSTL-2 (I and II), 1.5-V HSTL (I and II),
LVDS, LVPECL, Differential SSTL-18, Differential SSTL-2, Differential HSTL,
EP3SL70
27,000
67,500
54,000
2,214
56/56
4/34
150
422
288
104
22
48
56
6
1.8-V HSTL (I and II), PCI, PCI-X 1.0, LVTTL, LVCMOS
DDR3, DDR2, DDR, QDR II, RLDRAM II, SDR
Stratix III L FPGAs (1.1 V, 0.9 V)
Programmable Power Technology
EP3SL110
107,500
42,600
85,200
4,203
88/88
8/68
275
672
288
208
12
48
47
88
1.2, 1.5, 1.8, 2.5, 3.3
-2, -3, -4
16
3
3
3
3
EP3SL150
142,500
113,600
56,800
5,499
88/88
8/68
355
891
384
208
16
48
47
88
EP3SL200
198,900
159,120
112/112
79,560
12/96
1,250
9,396
468
576
208
112
36
88
66
EP3SL340
135,200
338,000
270,400
132/132
16,272
1,040
2,110
12/96
576
208
120
137
48
88