5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 48

• Manufacturer Part Number: 5M2210ZF256C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M2210ZF256C5N

• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 271
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 201.1MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of Gates: -
• Number Of I /o: 203
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Licensing
Development Kits
Getting started with the Nios II processor is now easier than ever. Not only
is the Nios II EDS free, but the Nios II economy core IP is also free.
As for the Nios II standard and fast core IP, licenses are available as a
standalone or as part of the Embedded IP Suite (IPS-EMBEDDED).
These royalty-free licenses never expire and allow you to target your
processor design on any Altera FPGA. The Embedded IP Suite is a value
bundle that contains licenses of the Nios II processor IP core, DDR1/2
Memory Controller IP core, Triple Speed Ethernet (TSE) MAC IP core,
and the NicheStack TCP/IP Network Stack, Nios II Edition software.
Go to page 58 for information about embedded development kits.
Nios II Embedded Processors
Hardware Development Tools
CPU Core Options
The Nios II processor family has three CPU core options with a common 32-bit instruction set architecture, binary code compatibility,
and the same software design suite. Choose the CPU appropriate for your designs, create multi-core systems to scale performance, or
break up software applications into simpler tasks.
*
• Quartus II design software
• Qsys system integration tools
• SignalTap II embedded logic analyzer plug-in for Nios II processor
• System console for low-level debug of Qsys systems
Embedded Processing
46
The Nios II/e processor is now available for free. No license is required.
Nios II Processor Family Members
Description
Pipeline
Multiplier
Branch prediction
Instruction cache
Data cache
Custom instructions
Altera Product Catalog
Features
•
2011
Optimized for maximum
performance; optional memory
management unit (MMU)
6 stage
1 cycle
Dynamic
Configurable
Configurable
Up to 256
Nios II/f (Fast) Processor
•
www.altera.com
Balanced cost and performance
5 stage
3 cycle
Static
Configurable
None
Up to 256
Nios II/s (Standard) Processor
Nios II C2H Compiler
Right-click to convert your ANSI-C
code into hardware accelerators in the
FPGA using the Nios II C2H Acceleration
Compiler. Accelerate Nios II embedded
software performance from 10X to 70X
without increasing clock frequency.
The tool automates the creation and
integration of hardware accelerators,
reducing development time from weeks
to minutes.
Optimized for minimum logic usage
1 stage
Emulated in software
None
None
None
Up to 256
Nios II/e (Economy) Processor*