5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 9

• Manufacturer Part Number: 5M2210ZF256C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M2210ZF256C5N

• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 271
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 201.1MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of Gates: -
• Number Of I /o: 203
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

1
2
3
4
See supported protocols and data rates on page 69
Available in industrial temperatures only (0
This is the base core logic register count. The ALM can support three registers when used in LUTREG mode, which increases total register count by an additional 50 percent.
The total transceiver count is the sum of 11.3-Gbps plus 8.5-Gbps plus 6.5-Gbps transceivers.
3.3-V compliant, requires a 3-V power supply.
ALMs
Equivalent LEs
Registers
M9K memory blocks
M144K memory blocks
MLAB memory (Kb)
Embedded memory (Kb)
18-bit x 18-bit multipliers
Speed grades
(fastest to slowest)
Global clock networks
Regional clock networks
Periphery clock networks
PLLs/unique outputs
Design security
HardCopy series device support
Configuration file size (Mb)
Others
I/O voltage levels supported (V)
I/O standards supported
Emulated LVDS channels,
1,100 Mbps
LVDS channels, 1,600 Mbps
(receive/transmit)
Embedded DPA circuitry
Series, parallel, and
differential OCT
Transceiver (SERDES) channels
(11.3 Gbps/8.5 Gbps/6.5 Gbps)
PCIe hard IP blocks
Memory devices supported
2
o
C to 100
4
o
C).
EP4S40G2
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15, Differential SSTL-18,
Differential SSTL-2, Differential HSTL-12, Differential HSTL-15, Differential HSTL-18, SSTL-15 (I and II),
12/12/12
228,000
182,400
91,200
14,283
SSTL-18 (I and II), SSTL-2 (I and II), 1.2-V HSTL (I and II), 1.5-V HSTL (I and II), 1.8-V HSTL (I and II)
1,235
2,850
1,288
8/68
192
64
88
95
22
2
EP4S40G5
12/12/12
212,480
531,200
424,960
20,736
Plug & Play Signal Integrity, Programmable Power Technology
1,280
1,024
6,640
8/68
112
172
256
Stratix IV GT FPGAs (0.95 V), 11.3-Gbps Transceivers
64
88
2
DDR3, DDR2, DDR, QDR II, RLDRAM II, SDR
EP4S100G2
228,000
182,400
24/0/12
91,200
14,283
1,235
2,850
1,288
8/68
192
1.2, 1.5, 1.8, 2.5, 3.3
22
64
88
95
2
-1, -2, -3
46/46
16
3
3
3
–
Altera Product Catalog
EP4S100G3
116,480
291,200
232,960
24/8/16
13,608
3,640
12/96
936
832
112
172
256
36
88
4
3
Stratix IV GT FPGA Features
EP4S100G4
•
141,440
353,600
282,880
24/8/16
18,144
2011
1,248
4,420
1,024
12/96
112
172
256
48
88
4
1
•
www.altera.com
EP4S100G5
212,480
531,200
424,960
32/0/16
20,736
Devices
1,280
6,640
1,024
12/96
112
172
256
64
88
4
7