5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 30

• Manufacturer Part Number: 5M2210ZF256C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M2210ZF256C5N

• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 271
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 201.1MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of Gates: -
• Number Of I /o: 203
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Devices
Cyclone V GX FPGA Features
28
1
2
Maximum LVDS channels, transceiver channels, PLLs, and PCIe hard IP blocks for the product line shown.Various packages offer a variety of options to meet your design needs.
3.3-V compliant, requires a 3-V power supply.
Altera Product Catalog
ALMs
Equivalent LEs
Registers
M10K memory blocks
M10K memory (Kb)
MLAB memory (Kb)
Variable-precision DSP blocks
18-bit x 18-bit multipliers
Speed grades: FPGA fabric
(fastest to slowest)
Speed grades: transceiver
(fastest to slowest)
Global clock networks
PLLs/unique outputs
Configuration file size (Mb)
Design security
I/O voltage levels
supported (V)
I/O standards supported
LVDS channels (875-Mbps
receive, 840-Mbps transmit)
Embedded DPA circuitry
Series and differential OCT
Programmable drive strength
Transceiver (SERDES)
channels (3.125 Gbps)
PCIe Gen2 x4 hard IP blocks
DDR3/2 hard memory
controller IP blocks
Memory devices
supported
•
2011
•
www.altera.com
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15, Differential SSTL-18,
Differential SSTL-2, Differential HSTL-12, Differential HSTL-15, Differential HSTL-18, SSTL-15 (I and II),
SSTL-18 (I and II), SSTL-2 (I and II), 1.2-V HSTL (I and II), 1.5-V HSTL (I and II), 1.8-V HSTL (I and II),
5CGXC3
25,000
37,736
9,434
1,170
0 or 1
0 or 1
117
147
TBD
40
80
16
48
5
3
Cyclone V GX FPGAs (1.1 V), 3.125-Gbps Transceivers
5CGXC4
50,000
75,472
18,868
0 or 2
2,850
0 or 1
TBD
285
295
140
100
70
16
6
6
See supported protocols and data rates on page 69
DDR3, DDR2, DDR, LPDDR, LPDDR2
1.1, 1.2, 1.5, 1.8, 2.5, 3.3
HiSpi, SLVS, Sub-LVDS
5CGXC5
113,208
-6, -7, -8
-6, -7, -8
28,302
75,000
0 or 1
0 or 2
4,510
TBD
451
442
132
264
100
16
3
3
3
6
6
–
5CGXC7
150,000
226,416
56,604
6,020
0 or 1
0 or 2
602
884
220
440
TBD
122
16
7
9
5CGXC9
113,208
300,000
452,832
12,460
1,246
1,769
0 or 1
0 or 2
TBD
406
812
122
16
12
8