5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 24

• Manufacturer Part Number: 5M2210ZF256C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M2210ZF256C5N

• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 271
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 201.1MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of Gates: -
• Number Of I /o: 203
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

1
2
Arria V GT FPGA Features
Devices
22
Maximum LVDS channels, transceiver channels, PLLs, and PCIe hard IP blocks for the product line shown.Various packages offer a variety of options to meet your design needs.
3.3-V compliant, requires a 3-V power supply.
Altera Product Catalog
ALMs
Equivalent LEs
Registers
M10K memory blocks
M10K memory (Kb)
MLAB memory (Kb)
Variable-precision DSP blocks
18-bit x 18-bit multipliers
Speed grades: FPGA fabric
(fastest to slowest)
Speed grades: transceiver
(fastest to slowest)
Global clock networks
PLLs/unique outputs
Configuration file size (Mb)
Design security
I/O voltage levels supported (V)
I/O standards supported
LVDS channels, 1,250 Mbps
(receive/transmit)
Embedded DPA circuitry
Series and differential OCT
Programmable drive strength
Transceiver (SERDES) channels
(10.3125 Gbps, 6.375 Gbps)
PCIe Gen2 x4 hard IP blocks
DDR3/2 hard memory controller IP blocks
Memory devices supported
•
2011
•
www.altera.com
Differential SSTL-18, Differential SSTL-2, Differential HSTL-12, Differential HSTL-15,
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15,
DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, LPDDR2, Mobile DDR, SDR
Differential HSTL-18, SSTL-15 (I and II), SSTL-18 (I and II), SSTL-2 (I and II),
Arria V GT FPGAs (1.1 V)
1.2-V HSTL (I and II), 1.5-V HSTL (I and II), 1.8-V HSTL (I and II)
5AGTD3
136,879
362,730
547,517
17,260
1,726
1,961
1,045
2,090
12/48
4, 12
TBD
120
See supported protocols and data rates on page 69
1
1
1.2, 1.5, 1.8, 2.5, 3.0, 3.3
1
, Up to 10.3125-Gbps Transceivers
16
-5
-3
3
3
3
3
2
5AGTD5
190,000
503,500
760,000
23,780
2,378
2,943
1,139
2,278
16/64
8,12
TBD
150
1
4