5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 32

• Manufacturer Part Number: 5M2210ZF256C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M2210ZF256C5N

• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 271
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 201.1MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of Gates: -
• Number Of I /o: 203
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Devices
Cyclone IV GX FPGA Features
1
2
3
30
Maximum LVDS channels, transceiver channels, PLLs, and PCIe hard IP blocks for the product line shown. Various packages offer a variety options to meet your design needs.
Transceiver performance varies by product line and package offering.
EP4CGX30 supports 3.125 Gbps only in F484 package option.
LEs
M9K memory blocks
Embedded memory (Kb)
18-bit x 18-bit multipliers
Speed grades
(fastest to slowest)
Global clock networks
PLLs/unique outputs
Configuration file size (Mb)
I/O voltage levels
supported (V)
I/O standards supported
Emulated LVDS channels
LVDS channels, 840 Mbps
(receive/transmit)
Transceiver (SERDES)
channels (2.5 Gbps/3.125 Gbps)
PCIe Gen1 hard IP blocks
Memory devices supported
Altera Product Catalog
•
2011
•
www.altera.com
EP4CGX15
-6,-7,-8
14,400
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15, Differential SSTL-18,
Differential SSTL-2, Differential HSTL-12, Differential HSTL-15, Differential HSTL-18, SSTL-15 (I and II),
3/15
540
3.8
7/7
2/0
SSTL-18 (I and II), SSTL-2 (I and II), 1.2-V HSTL (I and II), 1.5-V HSTL (I and II), 1.8-V HSTL (I and II)
60
20
0
9
EP4CGX22
-6,-7,-8
21,280
14/14
4/20
756
2/0,
7.6
4/0
84
40
20
40
Cyclone IV GX FPGAs (1.2 V)
EP4CGX30
-6,-7,-8
29,440
14/14
1,080
4/20
0/4
See supported protocols and data rates on page 69
120
4/0,
7.6
DDR2, DDR, QDR II, RLDRAM II, SDR
80
20
40
3
1.2, 1.5, 1.8, 2.5, 3.3
EP4CGX50
-6,-7,-8
49,888
2,502
49/49
8/40
24.5
278
140
0/8
30
73
1
1
, 3.125-Gbps Transceivers
EP4CGX75
-6,-7,-8
73,920
4,158
49/49
8/40
24.5
462
198
0/8
30
73
EP4CGX110
109,424
59/59
5,490
-7,-8
8/40
47.6
666
280
139
0/8
30
2
EP4CGX150
149,760
6,480
59/59
-7,-8
8/40
47.6
720
360
139
0/8
30