5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 8

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5M2210ZF256C5N

Manufacturer Part Number
5M2210ZF256C5N
Description
ALTERA
Manufacturer
Altera
Series
MAX Vr

Specifications of 5M2210ZF256C5N

Cpld Type
FLASH
No. Of Macrocells
1700
No. Of I/o's
271
Propagation Delay
7.5ns
Global Clock Setup Time
4.6ns
Frequency
201.1MHz
Supply Voltage Range
1.71V To 1.89V
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
2210
Number Of Macrocells
1700
Number Of Gates
-
Number Of I /o
203
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-LBGA
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Vendor undefined / RoHS Compliant

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0
1
2
Devices
Stratix V E FPGA Features
6
All data is preliminary.
3.3-V compliant, requires a 3-V power supply.
Altera Product Catalog
ALMs
Equivalent LEs
Registers
M20K memory blocks
M20K memory (Mb)
MLAB memory (Mb)
18-bit x 18-bit multipliers
27-bit x 27-bit DSP blocks
Speed grades: FPGA fabric
(fastest to slowest)
Global clock networks
Regional clock networks
Design security
HardCopy series device support
I/O voltage levels supported (V)
I/O standards supported
LVDS channels, 1.4 Gbps
(receive/transmit)
Embedded DPA circuitry
Series, parallel, and differential OCT
100GbE hard IP blocks
Memory devices supported
2
2011
www.altera.com
Differential SSTL-18, Differential SSTL-2, Differential HSTL-12, Differential HSTL-5, Differential
HSTL-18, SSTL-15 (I and II), SSTL-18 (I and II), SSTL-2 (I and II), 1.2-V HSTL (I and II),
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15,
1,268,000
317,000
840,000
5SEE9
2,640
9.67
704
352
210
52
DDR3, DDR2, DDR, QDR II, RLDRAM II, SDR
1.5-V HSTL (I and II), 1.8-V HSTL (I and II)
Stratix V E FPGAs (0.85 V)
1.2, 1.5, 1.8, 2.5, 3.3
-3, -4
No
16
92
3
3
3
3
2
1
1,434,000
358,500
950,000
5SEEB
2,640
12.12
704
352
210
52

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