AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 26

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
Mode 2: High Frequency Clock Distribution—CLK or
External VCO >1600 MHz
The AD9516 power-up default configuration has the PLL
powered off and the routing of the input set so that the CLK/
CLK input is connected to the distribution section through the
VCO divider (divide-by-2/divide-by-3/divide-by-4/divide-by-5/
divide-by-6). This is a distribution-only mode that allows for an
external input up to 2400 MHz (see
frequency that can be applied to the channel dividers is 1600 MHz;
therefore, higher input frequencies must be divided down before
reaching the channel dividers. This input routing can also be
used for lower input frequencies, but the minimum divide is 2
before the channel dividers.
When the PLL is enabled, this routing also allows the use of the
PLL with an external VCO or VCXO with a frequency <2400 MHz.
In this configuration, the external VCO/VCXO feeds directly
into the prescaler.
The register settings shown in Table 21 are the default values
of these registers at power-up or after a reset operation. If the
contents of the registers are altered by prior programming after
power-up or reset, these registers may also be set intentionally
to these values.
Table 3
). The maximum
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Table 21. Default Settings of Some PLL Registers
Register
0x010[1:0] = 01b
0x1E0[2:0] = 010b
0x1E1[0] = 0b
When using the internal PLL with an external VCO, the PLL
must be turned on.
Table 22. Settings When Using an External VCO
Register
0x010[1:0] = 00b
0x010 to 0x01D
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This
loop filter determines the loop bandwidth and stability of the
PLL. Make sure to select the proper PFD polarity for the VCO
being used.
Table 23. Setting the PFD Polarity
Register
0x010[7] = 0b
0x010[7] = 1b
Description
PLL normal operation (PLL on).
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and I
according to the intended loop configuration.
Description
PLL asynchronous power-down (PLL off )
Set VCO divider = 4
Use the VCO divider
Description
PFD polarity positive (higher control
voltage produces higher frequency)
PFD polarity negative (higher control
voltage produces lower frequency)
CP