AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 72

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
APPLICATION NOTES
USING THE AD9516 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock. Considering an ideal ADC of infinite
resolution where the step size and quantization error can be
ignored, the available SNR can be expressed approximately by
where:
f
t
Figure 57 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
See the AN-756 Application Note and the AN-501 Application
Note at www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9516 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions that
maximize converter SNR performance. The input requirements of
the ADC (differential or single-ended, logic level, and termination)
should be considered when selecting the best clocking/converter
solution.
A
J
is the rms jitter on the sampling clock.
is the highest analog frequency being digitized.
110
100
90
80
70
60
50
40
30
SNR
10
(dB)
Figure 57. SNR and ENOB vs. Analog Input Frequency
=
20
×
log
⎛
⎜
⎜
⎝
2
π
f
f
1
A
A
t
100
(MHz)
J
⎞
⎟
⎟
⎠
SNR = 20log
2πf
1
A
t
J
1k
18
16
14
12
10
8
6
Rev. 0 | Page 72 of 76
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9520 provide the lowest jitter
clock signals available from the AD9520. The LVPECL outputs
(because they are open emitter) require a dc termination to bias
the output transistors. The simplified equivalent circuit in
Figure 46 shows the LVPECL output stage.
In most applications, a LVPECL far-end Thevenin termination
(see Figure 58) or Y-termination (see Figure 59) is recommended.
In both cases, V
If it does not match, ac coupling is recommended (see Figure 60).
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the
case where VS_LVPECL = 2.5 V, the 50 Ω termination resistor
connected to ground in Figure 59 should be changed to 19 Ω.
VS_LVPECL
Figure 58. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
VS_LVPECL
VS_LVPECL
Figure 60. AC-Coupled LVPECL with Parallel Transmission Line
LVPECL
LVPECL
LVPECL
200Ω
Figure 59. DC-Coupled 3.3 V LVPECL Y-Termination
S
of the receiving buffer should match VS_LVPECL.
0.1nF
0.1nF
V
(NOT COUPLED)
200Ω
SINGLE-ENDED
T
= V
Z
Z
S
0
0
TRANSMISSION LINE
100Ω DIFFERENTIAL
50Ω
50Ω
– 1.3V
= 50Ω
= 50Ω
(COUPLED)
127Ω
83Ω
VS_LVPECL
50Ω
100Ω
V
50Ω
50Ω
127Ω
83Ω
S
= VS_LVPECL
VS_LVPECL
LVPECL
LVPECL
V
S
LVPECL