AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 2

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Absolute Maximum Ratings .......................................................... 15
Pin Configuration and Function Descriptions ........................... 16
Typical Performance Characteristics ........................................... 18
Terminology .................................................................................... 22
Detailed Block Diagram ................................................................ 23
Theory of Operation ...................................................................... 24
Power Supply Requirements ....................................................... 4
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 6
Clock Outputs ............................................................................... 6
Timing Characteristics ................................................................ 7
Clock Output Additive Phase Noise
(Distribution Only; VCO Divider Not Used) ........................... 9
Clock Output Absolute Time Jitter
(Clock Generation Using External VCXO) ............................ 10
Clock Output Additive Time Jitter
(VCO Divider Not Used) .......................................................... 10
Clock Output Additive Time Jitter (VCO Divider Used) ..... 11
Delay Block Additive Time Jitter .............................................. 11
Serial Control Port ..................................................................... 11
PD , SYNC , and RESET Pins ..................................................... 12
LD, STATUS, REFMON Pins.................................................... 12
Power Dissipation ....................................................................... 13
Thermal Resistance .................................................................... 15
ESD Caution ................................................................................ 15
Operational Configurations ...................................................... 24
Timing Diagrams ..................................................................... 8
Mode1: Clock Distribution or
External VCO < 1600 MHz .................................................. 24
Mode 2: High Frequency Clock Distribution—
CLK or External VCO >1600 MHz ..................................... 26
Phase-Locked Loop (PLL) .................................................... 28
Configuration of the PLL ...................................................... 28
Phase Frequency Detector (PFD) ........................................ 28
Charge Pump (CP) ................................................................. 29
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Serial Control Port ......................................................................... 45
Clock Distribution ..................................................................... 35
Reset Modes ................................................................................ 43
Power-Down Modes .................................................................. 43
Serial Control Port Pin Descriptions ....................................... 45
PLL External Loop Filter ....................................................... 29
PLL Reference Inputs ............................................................. 29
Reference Switchover ............................................................. 29
Reference Divider R ............................................................... 30
VCXO/VCO Feedback Divider N: P, A, B .......................... 30
Digital Lock Detect (DLD) ................................................... 31
Analog Lock Detect (ALD) ................................................... 31
Current Source Digital Lock Detect (CSDLD) .................. 31
External VCXO/VCO Clock Input (CLK/ CLK ) ................ 32
Holdover .................................................................................. 32
Manual Holdover Mode ........................................................ 32
Automatic/Internal Holdover Mode .................................... 33
Frequency Status Monitors ................................................... 34
Operating Modes.................................................................... 35
CLK Direct to LVPECL Outputs .......................................... 35
Clock Frequency Division ..................................................... 36
VCO Divider ........................................................................... 36
Channel Dividers—LVPECL Outputs ................................. 36
Channel Dividers—LVDS/CMOS Outputs ........................ 38
Synchronizing the Outputs—SYNC Function ................... 41
Clock Outputs ......................................................................... 42
LVPECL Outputs: OUT0 to OUT5 ..................................... 42
LVDS/CMOS Outputs: OUT6 to OUT9 ............................. 43
Power-On Reset—Start-Up Conditions When
VS Is Applied ............................................................................ 43
Asynchronous Reset via the RESET Pin ............................. 43
Soft Reset via 0x000[5] .......................................................... 43
Chip Power-Down via PD .................................................... 43
PLL Power-Down ................................................................... 44
Distribution Power-Down .................................................... 44
Individual Clock Output Power-Down ............................... 44
Individual Circuit Block Power-Down ................................ 44