AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 41

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Calculating the Fine Delay
The following values and equations are used to calculate the
delay of the delay block.
Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3;
001 = 2 + 1 = 3; 111 = 0 + 1 = 1.
Note that only delay fraction values up to 47 decimal (101111b;
0x02F) are supported.
In no case can the fine delay exceed one-half of the output clock
period. If a delay longer than half of the clock period is attempted,
the output stops clocking.
The delay function adds some jitter greater than that specified
for the nondelayed output. This means that the delay function
should be used primarily for clocking digital chips, such as FPGA,
ASIC, DUC, and DDC. An output with this delay enabled may
not be suitable for clocking data converters. The jitter is higher
for long full scales because the delay block uses a ramp and trip
points to create the variable delay. A slower ramp time produces
more time jitter.
I
Number of Capacitors = Number of Bits =
0 in Ramp Capacitors + 1
Delay Range (ns) = 200 × ((No. of Caps + 3)/(I
Delay Full Scale (ns) = Delay Range + Offset
Fine Delay (ns) =
Delay Range × Delay Fraction × (1/63) + Offset
Offset
RAMP
(μA) = 200 × (Ramp Current + 1)
( )
ns
=
0.34
+
(
1600
−
I
RAMP
)
×
10
−
4
+
⎛
⎜
⎜
⎝
RAMP
No.
)) × 1.3286
of
I
RAMP
Caps
Rev. 0 | Page 41 of 76
−
1
⎞
× ⎟ ⎟
⎠
6
Synchronizing the Outputs—SYNC Function
The AD9516 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions and subsequently releasing these
outputs to continue clocking at the same instant with the preset
conditions applied. This allows for the alignment of the edges of
two or more outputs or for the spacing of edges according to the
coarse phase offset settings for two or more outputs.
Synchronization of the outputs is executed in several ways:
•
•
•
•
•
The most common way to execute the SYNC function is to use
the SYNC pin to do a manual synchronization of the outputs.
This requires a low going signal on the SYNC pin, which is held
low and then released when synchronization is desired. The timing
of the SYNC operation is shown in
and
of up to one cycle of the clock at the input to the channel divider
due to the asynchronous nature of the SYNC signal with respect
to the clock edges inside the AD9516. The delay from the
rising edge to the beginning of synchronized output clocking is
between 14 and 15 cycles of clock at the channel divider input,
plus either one cycle of the VCO divider input (see
or one cycle of the CLK input (see
whether the VCO divider is used. Cycles are counted from the
rising edge of the signal.
Another common way to execute the SYNC function is by
setting and resetting the soft SYNC bit at 0x230[0] (see Table 47
through Table 57 for details). Both setting and resetting of the
soft SYNC bit require an update all registers (0x232[0] = 1)
operation to take effect.
Figure 45
The SYNC pin is forced low and then released (manual sync).
By setting and then resetting any one of the following three
bits: the soft SYNC bit (0x230[0]), the soft reset bit (0x000[5]
[mirrored]), and the power-down distribution reference bit
(0x230[1]).
Synchronization of the outputs can be executed as part of
the chip power-up sequence.
The RESET pin is forced low and then released (chip reset).
The PD pin is forced low and then released (chip power-down).
(VCO divider not used). There is an uncertainty
Figure 44
Figure 45
(using VCO divider)
), depending on
AD9516-5
Figure 44
SYNC
),