AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 11

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 9.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
DELAY BLOCK ADDITIVE TIME JITTER
Table 10.
Parameter
DELAY BLOCK ADDITIVE TIME JITTER
1
SERIAL CONTROL PORT
Table 11.
Parameter
CS (INPUT)
SCLK (INPUT)
This value is incremental; that is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
LVDS OUTPUT ADDITIVE TIME JITTER
CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;
100 MHz Output
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Divider = 12; Duty-Cycle Correction = Off
Divider = 12; Duty-Cycle Correction = Off
Divider = 12; Duty-Cycle Correction = Off
Delay (1600 μA, 1C) Fine Adjust 000000
Delay (1600 μA, 1C) Fine Adjust 101111
Delay (800 μA, 1C) Fine Adjust 000000
Delay (800 μA, 1C) Fine Adjust 101111
Delay (800 μA, 4C) Fine Adjust 000000
Delay (800 μA, 4C) Fine Adjust 101111
Delay (400 μA, 4C) Fine Adjust 000000
Delay (400 μA, 4C) Fine Adjust 101111
Delay (200 μA, 1C) Fine Adjust 000000
Delay (200 μA, 1C) Fine Adjust 101111
Delay (200 μA, 4C) Fine Adjust 000000
Delay (200 μA, 4C) Fine Adjust 101111
1
Min
2.0
2.0
Min
Min
Typ
110
2
110
2
Typ
210
285
350
Rev. 0 | Page 11 of 76
Max
0.8
3
0.8
1
Typ
0.54
0.60
0.65
0.85
0.79
1.2
1.2
2.0
1.3
2.5
1.9
3.8
Max
Unit
V
V
μA
μA
pF
V
V
μA
μA
pF
Max
Unit
fs rms
fs rms
fs rms
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
SCLK has an internal 30 kΩ pull-down resistor
Test Conditions/Comments
Distribution section only; does not include PLL; uses rising
edge of clock signal
Calculated from SNR of ADC method
Distribution section only; does not include PLL; uses rising
edge of clock signal
Calculated from SNR of ADC method
Distribution section only; does not include PLL; uses rising
edge of clock signal
Calculated from SNR of ADC method
Unit
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
Test Conditions/Comments
Incremental additive jitter
AD9516-5