AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 43

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For this reason, the LVPECL outputs have several power-down
modes. This includes a safe power-down mode that continues
to protect the output devices while powered down, although it
consumes somewhat more power than a total power-down. If
the LVPECL output pins are terminated, it is best to select the
safe power-down mode. If the pins are not connected (unused),
it is acceptable to use the total power-down mode.
LVDS/CMOS Outputs: OUT6 to OUT9
OUT6 to OUT9 can be configured as either an LVDS differential
output or as a pair of CMOS single-ended outputs. The LVDS
outputs allow for selectable output current from ~1.75 mA to ~7 mA.
The LVDS output polarity can be set as noninverting or inverting,
which allows for the adjustment of the relative polarity of outputs
within an application without requiring a board layout change. Each
LVDS output can be powered down if not needed to save power.
OUT6 to OUT9 can also be CMOS outputs. Each LVDS output
can be configured to be two CMOS outputs. This provides for
up to eight CMOS outputs: OUT6A, OUT6B, OUT7A, OUT7B,
OUT8A, OUT8B, OUT9A, and OUT9B. When an output is
configured as CMOS, the CMOS Output A is automatically
turned on. The CMOS Output B can be turned on or off
independently. The relative polarity of the CMOS outputs can also
be selected for any combination of inverting and noninverting. See
Table 52, 0x140[7:5], 0x141[7:5], 0x142[7:5], and 0x143[7:5].
Each LVDS/CMOS output can be powered down as needed to
save power. The CMOS output power-down is controlled by the
same bit that controls the LVDS power-down for that output.
This power-down control affects both the CMOS A and CMOS B
outputs. However, when the CMOS A output is powered up, the
CMOS B output can be powered on or off separately.
Figure 47. LVDS Output Simplified Equivalent Circuit with
Figure 46. LVPECL Output Simplified Equivalent Circuit
3.5 mA Typical Current Source
3.5mA
3.5mA
GND
3.3V
OUT
OUT
OUT
OUT
Rev. 0 | Page 43 of 76
RESET MODES
The AD9516 has several ways to force the chip into a reset
condition that restores all registers to their default values and
makes these settings active.
Power-On Reset—Start-Up Conditions When VS Is Applied
A power-on reset (POR) is issued when the VS power supply is
turned on. The POR pulse duration is <100 ms and initializes
the chip to the power-on conditions that are determined by the
default register settings. These are indicated in the Default Value
(Hex) column of Table 47. At power-on, the AD9516 also executes
a SYNC operation, which brings the outputs into phase alignment
according to the default settings. It is recommended that the
user not toggle SCLK during the reset pulse.
Asynchronous Reset via the RESET Pin
An asynchronous hard reset is executed by momentarily pulling
RESET low. A reset restores the chip registers to the default settings.
It is recommended that the user not toggle SCLK for 20 ns after
RESET goes high.
Soft Reset via 0x000[5]
A soft reset is executed by writing 0x000[5] and 0x000[2] = 1b.
This bit is not self-clearing; therefore, it must be cleared by writing
0x000[5] and 0x000[2] = 0b to reset it and complete the soft reset
operation. A soft reset restores the default values to the internal
registers. The soft reset bit does not require an update registers
command (0x232 = 0x01) to be issued.
POWER-DOWN MODES
Chip Power-Down via PD
The AD9516 can be put into a power-down condition by pulling
the PD pin low. Power-down turns off most of the functions and
currents inside the AD9516. The chip remains in this power-down
state until PD is brought back to logic high. When woken up, the
AD9516 returns to the settings programmed into its registers
prior to the power-down, unless the registers are changed by
new programming while the PD pin is held low.
The PD power-down shuts down the currents on the chip, except
the bias current necessary to maintain the LVPECL outputs in a
safe shutdown mode. This is needed to protect the LVPECL output
circuitry from damage that can be caused by certain termination
and load configurations when tristated. Because this is not a
complete power-down, it can be called sleep mode.
Figure 48. CMOS Equivalent Output Circuit
V
S
OUT1/
OUT1
AD9516-5