AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 13

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
REF1, REF2, AND CLK FREQUENCY STATUS MONITOR
LD PIN COMPARATOR
POWER DISSIPATION
Table 14.
Parameter
POWER DISSIPATION, CHIP
POWER DELTAS, INDIVIDUAL FUNCTIONS
Normal Range
Extended Range
Trip Point
Hysteresis
Power-On Default
Full Operation; CMOS Outputs at 225 MHz
Full Operation; LVDS Outputs at 225 MHz
PD Power-Down
PD Power-Down, Maximum Sleep
VCP Supply
AD9516 Core
VCO Divider
REFIN (Differential)
REF1, REF2 (Single-Ended)
PLL
Channel Divider
LVPECL Channel (Divider Plus Output Driver)
LVPECL Driver
LVDS Channel (Divider Plus Output Driver)
LVDS Driver
Min
Min
1.02
8
Typ
1.0
1.5
1.5
75
31
4
220
30
20
4
75
30
120
90
140
50
Typ
1.6
260
Rev. 0 | Page 13 of 76
Max
1.2
2.1
2.1
185
4.8
Max
Unit
W
W
W
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Unit
MHz
kHz
V
mV
Test Conditions/Comments
The values in this table include all power supplies, unless
otherwise noted; the power deltas for individual drivers are
at dc; see Figure 7, Figure 8, and Figure 9 for power dissipation
vs. output frequency
No clock; no programming; default register values; does
not include power dissipated in external resistors; this
configuration has the following blocks already powered up:
VCO divider, six channel dividers, three LVPECL drivers, and
two LVDS drivers
f
six LVPECL outputs @ 562.5 MHz; eight CMOS outputs (10 pF
load) @ 225 MHz; all 4 fine delay blocks on, maximum current;
does not include power dissipated in external resistors
f
LVPECL outputs @ 562.5 MHz; four LVDS outputs @ 225 MHz;
all 4 fine delay blocks on: maximum current; does not include
power dissipated in external resistors
PD pin pulled low; does not include power dissipated in
terminations
PD pin pulled low; PLL power-down 0x010[1:0] = 01b; SYNC
power-down 0x230[2] = 1b; REF for distribution power-down
0x230[1] = 1b
PLL operating; typical closed-loop configuration (this
number is included in all other power measurements)
AD9516 core only, all drivers off, PLL off, VCO divider off, and
delay blocks off; the power consumption of the configuration
of the user can be derived from this number and the power
deltas that follow
Power delta when a function is enabled/disabled
VCO divider on/off
All references off to differential reference enabled
All references off to REF1 or REF2 enabled; differential
reference not enabled
PLL off to PLL on, normal operation; no reference enabled
Divider bypassed to divide-by-2 to divide-by-32
No LVPECL output on to one LVPECL output on (that is,
enabling OUT0 with OUT1 off; Divider 0 enabled)
Second LVPECL output turned on, same channel (that is,
enabling OUT0 with OUT1 already on)
No LVDS output on to one LVDS output on (that is, enabling
OUT8 with OUT9 off with Divider 4.1 enabled and Divider 4.2
bypassed)
Second LVDS output turned on, same channel (that is,
enabling OUT8 with OUT9 already on)
CLK
CLK
= 2.25 GHz; VCO divider = 2; all channel dividers on;
= 2.25 GHz; VCO divider = 2; all channel dividers on; six
Test Conditions/Comments
Frequency above which the monitor indicates the
presence of the reference
Frequency above which the monitor indicates the
presence of the reference
AD9516-5