ADSP-BF531SBBC400 Analog Devices Inc, ADSP-BF531SBBC400 Datasheet - Page 12

• Manufacturer Part Number: ADSP-BF531SBBC400
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF531SBBC400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 52kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: CSPBGA
• Package: 160CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Device Million Instructions Per Second: 400 MIPS
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/BF532/BF533
17.
18.
19.
DESCRIPTION:
In multichannel mode, the SPORT's MRCS registers are used to select which channels are active (transmitted or received) and which ones
are to be ignored. For each ignored channel, the DT output will be three-stated. The problem is seen when "Multichannel DMA packing"
is disabled. In this mode, for the inactive channels, the most significant BIT (MSB) of the data word will be driven on the DT line and,
correspondingly, the TFS will be driven high for the duration of one bit to indicate valid data.
WORKAROUND:
A possible workaround is to enable "Multichannel DMA packing". In this mode, only active channels are DMA'ed from/into memory, and
the inactive channels will effectively be blanked out. However, in this mode, it is not possible to dynamically change the active/inactive
channels as in the non-packed DMA mode, so it may not be feasible for all applications.
APPLIES TO REVISION(S):
0.3, 0.4
DESCRIPTION:
An external RFS is not ignored during an active frame. This can result in the transfer of data stopping.
The same problem can occur with internal frame syncs if RFSDIV is programmed to a value less than the window size.
WORKAROUND:
Avoid external frame syncs while the current frame is active. Do not program the RFSDIV to a value less than the window size.
APPLIES TO REVISION(S):
0.3
DESCRIPTION:
For this problem to occur, the processor must perform a data memory read of a non-cacheable or write-through cacheable L2 or external
memory address that was recently written. The "recent write" must currently be held in the write buffer when it is read again. The read
must be executed during the same clock cycle that this "recent write" drains from the write buffer to the destination memory location.
Immediately prior to the read of the "recent write", a dual-DAG access must be executed. Dual-DAG accesses must collide with each
other, but may have any relationship with the "recent write" address.
Immediately following the read of the "recent write", there must not be a read, write, or prefetch (else this anomaly is avoided).
Note: A dual-DAG collision is if both DAGs access the same sub-bank in L1 memory or L1 cache.
WORKAROUND:
1) Avoid reads of recently written L2 addresses immediately after colliding dual-DAG accesses.
OR
2) Precede the offensive dual-DAG/L2 read instructions with a SSYNC to insure the previous write is no longer in the write buffer.
OR
3) Configure all L2 as write-back cacheable (avoids using the write-buffers).
The VisualDSP++ Blackfin compiler includes a workaround for this hardware anomaly. The compiler will automatically enable the
workaround for the appropriate silicon revisions and parts, or the workaround can be enabled manually by specifying the compiler flag '-
workaround infinite-stall-202'. When enabled, the compiler will insert a PREFETCH[SP] instruction to avoid the anomaly conditions.
The macro __WORKAROUND_INFINITE_STALL_202 will be defined at compile, assemble, and link stages when the workaround is enabled.
APPLIES TO REVISION(S):
0.3, 0.4
05000200 - SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions:
05000201 - Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode:
05000202 - Possible Infinite Stall with Specific Dual-DAG Situation:
NR003532D | Page 12 of 45 | July 2008
Silicon Anomaly List