ADSP-BF531SBBC400 Analog Devices Inc, ADSP-BF531SBBC400 Datasheet - Page 20

• Manufacturer Part Number: ADSP-BF531SBBC400
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF531SBBC400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 52kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: CSPBGA
• Package: 160CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Device Million Instructions Per Second: 400 MIPS
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/BF532/BF533
36.
APPLIES TO REVISION(S):
0.3, 0.4
DESCRIPTION:
The anomaly is only an issue if there is a load which may access reserved or illegal memory on the opposite control flow of a conditional
jump to the taken path. The following sequences demonstrate how this anomaly can appear:
Sequence #1:
For the "predicted not taken" branch, the three instruction slots following the branch should not contain accesses which might cause a
hardware error:
Sequence #2:
For the "predicted taken" branch, the one instruction slot at the destination of the branch should not contain an access which might
cause a hardware error:
WORKAROUND:
If you are programming in assembly, it is necessary to avoid the conditions described above.
The VisualDSP++ Blackfin compiler includes a workaround for this hardware anomaly. The compiler will automatically enable the
workaround for the appropriate silicon revisions and part numbers, or you can enable the workaround manually by specifying the
compiler flag '-workaround speculative-loads'.
With the workaround enabled, the compiler will insert nops to avoid the anomaly condition.
The macro __WORKAROUND_SPECULATIVE_LOADS will be defined at compile, assemble and link build phases when the workaround is
enabled.
There are various checks in the compiler which avoid over-applying this workaround. For example, before the workaround is applied, it
ensures that the load is:
• not through SP or FP (in which case to stack and not illegal)
• not to a volatile qualified type address (in which case to a known legal address)
• to an address unknown to the compiler
• not duplicated in the branch targets (in which case must be ok to execute speculatively)
• not executed previous to the jump (in which case must be ok to execute speculatively)
The VisualDSP++ run-time libraries also avoid this anomaly for appropriate silicon revisions and part numbers.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5, 0.6
05000245 - Spurious Hardware Error from an Access in the Shadow of a Conditional Branch:
BRCC X [predicted not taken]
r0 = [p0];
r1 = [p1];
r2 = [p2];
BRCC X (bp)
Y: ...
X: r0 = [p0];
...
// If any of these three loads accesses non-existent
// memory, such as external SDRAM when the SDRAM
// controller is off, then a hardware error will result.
// If this instruction accesses non-existent memory,
// such as external SDRAM when the SDRAM controller
// is off, then a hardware error will result
NR003532D | Page 20 of 45 | July 2008
Silicon Anomaly List