ADSP-BF531SBBC400 Analog Devices Inc, ADSP-BF531SBBC400 Datasheet - Page 15

• Manufacturer Part Number: ADSP-BF531SBBC400
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF531SBBC400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 52kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: CSPBGA
• Package: 160CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Device Million Instructions Per Second: 400 MIPS
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

Silicon Anomaly List
25.
26.
27.
DESCRIPTION:
During a UART TX interrupt, if the IIR register is read and the THR register is not written to (to clear the TX interrupt), the UART TX interrupt
is masked. This can happen in an ISR if the end of the string is reached. In this case, disabling and enabling the ETBEI bit has no effect on
the state of the interrupt enable, but it should.
WORKAROUND:
Clear the ETBEI bit within the UART TX interrupt to end a string, and then execute an RTI. To re-enable the interrupt, simply set the ETBEI
bit. This will take the processor directly into the UART TX interrupt service routine when the THR register is empty.
APPLIES TO REVISION(S):
0.3, 0.4
DESCRIPTION:
If the NMI pin is asserted at boot time, the boot process will fail because there is no handler in the boot ROM. The behavior is not
predictable.
WORKAROUND:
Do not assert the NMI pin during a boot sequence.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5, 0.6
DESCRIPTION:
The duration of the start-bit in a word transmitted by the UART interface is incorrect.
For Clock Divisor values greater than 1 (as determined by the UART_DLL and UART_DLH registers), the pulse width can assume values of
14/16th or 15/16th of the nominal bit time.
Data, Parity and Stop bits have proper duration. The data will be correctly received.
See anomalies 05000230 and 05000231 regarding UART timing.
WORKAROUND:
None
APPLIES TO REVISION(S):
0.3, 0.4
05000215 - UART TX Interrupt Masked Erroneously:
05000219 - NMI Event at Boot Time Results in Unpredictable State:
05000225 - Incorrect Pulse-Width of UART Start Bit:
NR003532D | Page 15 of 45 | July 2008
ADSP-BF531/BF532/BF533