ADSP-BF531SBBC400 Analog Devices Inc, ADSP-BF531SBBC400 Datasheet - Page 40

• Manufacturer Part Number: ADSP-BF531SBBC400
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF531SBBC400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 52kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: CSPBGA
• Package: 160CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Device Million Instructions Per Second: 400 MIPS
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

ADSP-BF531/BF532/BF533
69.
70.
DESCRIPTION:
When the PPI is configured to trigger on a single external frame sync, all of the transfers require an edge on the frame sync except for the
first transfer. For the first transfer only, the frame sync input is level-sensitive. This will make the PPI begin a transfer if the frame sync is at
the active state, which can cause the PPI to start prematurely.
This anomaly does not apply when the PPI uses 2 or 3 frame syncs.
WORKAROUND:
When using a single external frame sync with the PPI, ensure that the frame sync is in the inactive state when the PPI is enabled.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5
DESCRIPTION:
Consider the following sequence:
1) System MMR write is stalled.
2) Interrupt occurs while the System MMR write is stalled (thus killing the write).
3) Interrupt Service Routine accesses (either read or write) any system MMR.
In order for this anomaly to happen, the interrupt must kill the write in one particular stage of the execution pipeline. In this case, the
anomaly will cause the MMR logic to think that the killed System MMR access is still valid. The following access (read/write) to the System
MMR in the ISR will cause the previously stalled write to complete erroneously.
Similarly, if the System MMR write is killed by an instruction itself, such a conditional branch, the erroneous write can happen if the store
buffer is full and emptying out to slow external memory.
NOTE: if the processor is halted in the ISR before the next System MMR access via the debugging tools, the processor will stall indefinitely
waiting for the write to complete, thus locking out the Emulation event.
WORKAROUND:
The workaround is to reset the MMR logic with another killed System MMR access in the branch's shadow. For example, setting up a read
from the System MMR CHIPID register and subsequently killing it will create a killed access that has no other side-effects on the system.
Therefore, the following code snippet, executed at the beginning of each ISR, will work around this anomaly:
In the case of System MMR writes being killed by the conditional branches, it is sufficient to insert 2 NOPs or any other non-MMR
instructions in the location immediately after the conditional branch.
NOTE: in order to prevent lock-ups during debug sessions, always insert a desired breakpoint after the above code snippet if you need to
halt the processor in the ISR.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5
05000313 - PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes:
05000315 - Killed System MMR Write Completes Erroneously on Next System MMR Access:
cc = r0 == r0;
if cc jump skip;
W[p0] = r1.l;
skip: ...
cc = r0 == r0;
p0.h = 0xffc0;
p0.l = 0x0014;
if cc jump skip; // always skip System MMR access, but it is fetched and killed
r0 = [p0];
skip: ...
// always true
// System MMR access is fetched and killed
// always true
// System MMR space CHIPID
// bogus System MMR read to work around the anomaly
// continue with ISR
NR003532D | Page 40 of 45 | July 2008
Silicon Anomaly List