ADSP-BF531SBBC400 Analog Devices Inc, ADSP-BF531SBBC400 Datasheet - Page 35

• Manufacturer Part Number: ADSP-BF531SBBC400
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF531SBBC400

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP, UART
• Clock Rate: 400MHz
• Non-volatile Memory: ROM (1 kB)
• On-chip Ram: 52kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Device Core Size: 16b
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Mips: 400
• Device Input Clock Speed: 400MHz
• Operating Supply Voltage (typ): 1.2/1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8/1.75V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: CSPBGA
• Package: 160CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Device Million Instructions Per Second: 400 MIPS
• For Use With: ADZS-BF533-EZLITE - KIT W/BOARD EVAL FOR ADSP-BF533
• Lead Free Status / Rohs Status: Not Compliant

Silicon Anomaly List
61.
62.
DESCRIPTION:
The SPORT receives incorrect data if it is configured as follows:
1) The secondary receive data is enabled (RXSE=1) or the word length > 16 bits.
AND
2) The RX FIFO is filled with 8 words of data.
AND
3) An additional word is clocked into the SPORT.
In this case, the overflow does not assert because there is room to hold the data. The overflow will assert if the next piece of data is
received without removing data from the FIFO.
This anomaly will cause one piece of primary data to be received in place of secondary data (RxSEC=1) or word swap (SLEN>0xF).
Subsequent words will be received correctly.
WORKAROUND:
Avoid the conditions described in the problem description.
Operating so closely to a FIFO overflow should be avoided.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5
DESCRIPTION:
When MemDMA source and destination descriptors are in different memory spaces (one in internal memory and one in external
memory), and if the traffic control is turned on, then the source descriptor count of descriptor words currently fetched can get corrupted
by the value in the current destination descriptor count (which can be greater or less than the original source descriptor count). This will
make the source fetch more/less descriptor elements than intended.
One possible result is that some elements of the descriptor may not be loaded. Another possible result is that extra descriptor element
fetches may be performed. The descriptor element pointer may also overflow and wrap back to the start of the register set if too many
extra fetches occur, thus overwriting good data with bad data in the first few registers (e.g., Next Descriptor Pointer). In this last case, the
DMA may not appear to fail until the next descriptor fetch, when it fetches an invalid pointer.
WORKAROUND:
Place source and destination descriptors in the same memory space. Both should be located either in external or internal memory.
APPLIES TO REVISION(S):
0.3, 0.4, 0.5
05000288 - SPORTs May Receive Bad Data If FIFOs Fill Up:
05000301 - Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space:
NR003532D | Page 35 of 45 | July 2008
ADSP-BF531/BF532/BF533