ADUC7122BBCZ-RL Analog Devices Inc, ADUC7122BBCZ-RL Datasheet - Page 90

• Manufacturer Part Number: ADUC7122BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7122BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x12b, D/A 12x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7122BBCZ-RL; ADUC7122BBCZ-RLTR

ADuC7122
Table 168. T3CON MMR Bit Designations
Bit
16:9
8
7
6
5
4
3:2
1
0
Value
1
0
1
0
1
0
1
0
1
0
00
01
10
11
1
0
1
0
These bits are reserved and should be written as 0s by user code.
Timer3 clock (32.768 kHz) prescaler.
Reserved.
Reserved.
Reserved.
Description
Count up/down enable.
Set by user code to configure Timer3 to count up.
Cleared by user code to configure Timer3 to count down.
Timer3 enable.
Set by user code to enable Timer3.
Cleared by user code to disable Timer3.
Timer3 operating mode.
Set by user code to configure Timer3 to operate in periodic mode.
Cleared by user to configure Timer3 to operate in free-running mode.
Watchdog timer mode enable.
Set by user code to enable watchdog mode.
Cleared by user code to disable watchdog mode.
Secure clear bit.
Set by the user to use the secure clear option.
Cleared by the user to disable the secure clear option by default.
Source clock/1 (default).
Watchdog timer IRQ enable.
Set by the user code to produce an IRQ instead of a reset when the watchdog reaches 0.
Cleared by the user code to disable the IRQ option.
PD_OFF.
Set by user code to stop Timer3 when the peripherals are powered down via Bits[6:4] in the POWCON MMR.
Cleared by user code to enable Timer3 when the peripherals are powered down via Bits[6:4] in the POWCON MMR.
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