CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 108

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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17.7.9
The ACCR register is used to control the bit timing of the au-
dio interface. After reset, this register is clear.
CSS
FCPRS
BCPRS
17.7.10 Audio DMA Control Register (ADMACR)
The ADMACR register is used to control the DMA support
of the audio interface. In addition, it is used to configure the
automatic transmission of the audio control bits. After reset,
this register is clear.
RMD
15
15
7
7
Reserved
Audio Clock Control Register (ACCR)
TMD
The Clock Source Select bit selects one out of
two possible clock sources for the audio inter-
face. After reset, the CSS bit is clear.
0 – The Aux1 clock is used to clock the Audio
1 – The 48-MHz USB clock is used to clock
The Frame Clock Prescaler is used to divide
the bit clock to generate the frame clock for
the receive and transmit operations. The bit
clock is divided by (FCPRS + 1). After reset,
the FCPRS field is clear. The maximum al-
lowed bit clock rate to achieve an 8 kHz frame
clock is 1024 kHz. This value must be set cor-
rectly even if the frame sync is generated ex-
ternally.
The Bit Clock Prescaler is used to divide the
audio interface clock (selected by the CSS bit)
to generate the bit clock for the receive and
transmit operations. The audio interface input
clock is divided by (BCPRS + 1). After reset,
the BCPRS[7:0] bits are clear.
The Receive Master DMA field specify which
slots (audio channels) are supported by DMA,
i.e. when a DMA request is asserted to the
DMA controller. If the RMDn bit is set for an
assigned slot n (RXDSAn = 1), a DMA request
n is asserted, when the ARDRn is full. If the
RXDSAn bit for a slot is clear, the RMDn bit is
13
Interface.
the Audio Interface.
FCPRS
12
4
BCPRS
ACO
11
3
10
RMD
ACD
1
CSS
0
8
0
8
108
TMD
ACD
ACO
17.8
When the Advanced Audio Interface is active, it can lock up
if the receive FIFO is cleared by writing 1 to the AGCR.CRF
bit, the transmit FIFO is cleared by writing 1 to the
AGCR.CTF bit, or the module is disabled by clearing the
AGCR.AAIEN bit.
Follow this procedure to disable the Advanced Audio Inter-
face:
1. Clear the ARSCR.RXSA and ATSCR.TXSA fields.
2. Wait at least 10 receive/transmit clock cycles.
3. Clear the AGCR.AAIEN bit.
USAGE HINTS
ignored. The following table shows the receive
DMA request scheme.
The Transmit Master DMA field specifies
which slots (audio channels) are supported by
DMA, i.e. when a DMA request is asserted to
the DMA controller. If the TMD bit is set for an
assigned slot n (TXDSAn = 1), a DMA request
n is asserted, when the ATDRn register is
empty. If the TXDSA bit for a slot is clear, the
TMD bit is ignored. The following table shows
the transmit DMA request scheme.
The Audio Control Data field is used to fill the
remaining bits of a 16-bit slot if only 13, 14, or
15 bits of PCM audio data are transmitted.
The Audio Control Output field controls the
number of control bits appended to the PCM
data word.
00 – No Audio Control bits are appended.
01 – Append ACD0.
10 – Append ACD1:0.
11 – Append ACD2:0.
RMD
0000
0001
0010
0011
0000
0001
0010
0011
TMD
x1xx
1xxx
x1xx
1xxx
DMA Request Condition
DMA Request Condition
ARDR0 full or ARDR1 full
Not supported on
Not supported on
ATDR0 empty or
ATDR0 empty
ATDR1 empty
ATDR1 empty
ARDR0 full
ARDR1 full
CP3BT10
CP3BT10
None
None