CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 208

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

www.national.com
29.0 Revision History
10/16/02
11/11/02
11/21/02
11/14/03
8/15/02
9/26/02
10/8/02
1/13/03
5/20/03
8/5/02
Date
Split the CP3BT10/CP3BT13 data sheet
into separate data sheets for each chip.
Added description of RDPROT field.
Clarified conditions for software DMA
transfer request in Section 9.4. Removed
commercial temperature range device.
Changed I/O Zone bus width to allow 8 bits.
Removed UART synchronous mode.
Changed flash programming sequence to
remove checking FMBUSY after each row.
Corrections to flash memory programming
sequence and MFT block diagrams.
Numerous minor corrections. Added more
description to AAI section. Added external
reset circuit. Fixed problems with figures.
Converted to new data sheet format.
Removed TB functionality from MFT
section.
Removed erroneous warning to always
write the IOCFG register with bit 1 set.
Alternate clock source for Advanced Audio
Interface changed to Aux1 clock. Changed
warning about clock glitches to say
Microwire interface must be disabled when
modifying bits in MWCTL1 register.
Changed bit settings which occur in step 2
of the sequence of ACCESS.bus slave
mode address match or global match.
Timer Mode Control Register bit 3 is
reserved and bit 2 is TAEDG. Bit 7 is the
TEN bit (a bit description has been added).
Polarity of all of the bits in the INTCTL
register has been inverted.
Updated DC specifications. Fixed errors in
Microwire bit and pin names. Changed
UART pin names to TXD and RXD. Added
Section 11.6 “Auxiliary Clocks”. Changed
diagram of I/O Port Pin Logic (Section 14).
Defined valid range of SCDV field in
Microwire/SPI module. Noted default
PRSSC register value generates a Slow
Clock frequency slightly higher than 32768
Hz. Clarified usage of CVSTAT register bits
and fields in CVSD/PCM module. Updated
layout of Bluetooth LLC registers. Added
usage hint for avoiding ACCESS.bus
module bus error.
Table 67 Revision History
Major Changes From Previous Version
208
2/28/04
3/16/04
5/20/04
6/23/04
7/16/04
8/24/04
7/3/04
9/7/04
4/4/05
Date
Table 67 Revision History (Continued)
Changed NSID designations in the product
selection guide. Updated Bluetooth section
for LMX5251 and LMX5252 radio chips.
Added BTSEQ[3:1] signals to pin
descriptions, GPIO alternate functions, and
package pin assignments. Changed CVSD
Conversion section. Changed definition of
the RESOLUTION field of the CVSD
Control register (CVCTRL). Changed DC
specification for Vxl2.
Changed LMX5251 interface circuit.
Updated DC specifications Iccid and Iccq.
Moved revision history in front of physical
dimensions. Changed back page
disclaimers.
Changed absolute maximum supply voltage
to 3.6V. Changed processor selection guide
table.
Changed footnote b in DC specs. Changed
product selection guide table.
Changed product selection guide table.
Added AC timing specifications for GPIO.
Deleted AC timing section for UART.
In Section 17.2, added sentence that an
external frame sync must be used in
asynchronous mode. In Section 12, in
several places noted that Idle and Halt
modes may only be entered from Active
mode, and the DHC and DMC bits must be
set when entering Idle and Halt modes.
Added usage hints Section 17.8. Removed
Section 21.4.1.
Added new reset circuits. Added note about
fluctuations in response due to SDI activity.
New back page.
Major Changes From Previous Version