CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 29

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

6.4.5
The SZCFG2 register is a word-wide, read/write register
that controls the timing and bus characteristics for off-chip
accesses selected with the SEL2 output signal.
At reset, the register is initialized to 069Fh. The register for-
mat is shown below.
WAIT
HOLD
RBE
WBR
BW
FRE
IPST
IPRE
BW
15
7
WBR
Static Zone 2 Configuration Register (SZCFG2)
Reserved
6
The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG2.FRE bit is set.
The Memory Hold field specifies the number
of T hold clock cycles used for each memory
access, ranging from 00b for no T hold cycles
to 11b for three T hold clock cycles. These bits
are ignored if the SZCFG2.FRE bit is set.
The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. This bit is ignored when
the
SZCFG2.BW is clear.
0
1
The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
bit is ignored, when SZCFG2.FRE bit is set or
when SZCFG2.RBE is clear.
0
1
The Bus Width bit controls the bus width of the
zone.
0
1
The Fast Read Enable bit controls whether
fast read bus cycles are used. A fast read op-
eration takes one clock cycle. A normal read
operation takes at least two clock cycles.
0
1
The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone.
0
1
The Preliminary Idle bit controls whether an
idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a dif-
ferent zone.
0
1
–
–
–
–
–
–
–
–
–
–
–
–
RBE
5
Burst read disabled.
Burst read enabled.
No TBW on burst read cycles.
One TBW on burst read cycles.
8-bit bus width.
16-bit bus width.
Normal read cycles.
Fast read cycles.
No idle cycle.
Idle cycle inserted.
No idle cycle.
Idle cycle inserted.
SZCFG2.FRE
12
4
HOLD
FRE
11
3
bit
IPRE IPST
10
2
is
WAIT
set
9
or
Res.
0
8
the
29
6.5
The number of wait cycles and hold cycles inserted into a
bus cycle depends on whether it is a read or write operation,
the type of memory or I/O being accessed, and the control
register settings.
6.5.1
When the CPU accesses the Flash program and data mem-
ory (address ranges 000000h
0E1FFFh), the number of added wait and hold cycles de-
pends on the type of access and the BIU register settings.
In fast-read mode (SZCFG0.FRE=1), a read operation is a
single cycle access. This limits the maximum CPU operat-
ing frequency to 24 MHz.
For
(SZCFG0.FRE=0), the number of inserted wait cycles is
specified in the SZCFG0.WAIT field. The total number of
wait cycles is the value in the WAIT field plus 1, so it can
range from 1 to 8. The number of inserted hold cycles is
specified in the SCCFG0.HOLD field, which can range from
0 to 3.
For a write operation in fast read mode (SZCFG0.FRE=1),
the number of inserted wait cycles is 1. No hold cycles are
used.
For a write operation normal read mode (SZCFG0.FRE=0),
the number of wait cycles is equal to the value written to the
SZCFG0.WAIT field plus 1 (in the late write mode) or 2 (in
the early write mode). The number of inserted hold cycles is
equal to the value written to the SCCFG0.HOLD field, which
can range from 0 to 3.
6.5.2
Read and write accesses to on-chip RAM is performed with-
in a single cycle, without regard to the BIU settings. The
RAM address is in the range of 0E 8000h
C000h
6.5.3
When the CPU accesses on-chip peripherals in the range of
0E F000h
cycle and one preliminary idle cycle is used. No hold cycles
are used. The IOCFG register determines the access timing
for the address range FF FB00h
–
a
0E EBFFh.
WAIT AND HOLD STATES
Flash Program/Data Memory
RAM Memory
Access to Peripherals
–
0E F1FFh and FF 0000h
read
operation
–
–
in
03FFFFh and 0E0000h
FF FBFFh.
–
normal-read
FF FBFFh, one wait
–
0E 91FFh and 0E
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mode
–