CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 120

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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19.3.7
The USTAT register is a byte-wide, read-only register that
contains the receive and transmit status bits. This register is
cleared upon reset. Any attempt by software to write to this
register is ignored. The register format is shown below.
UPE
UFE
UDOE
UERR
UBKD
URB9
Res.
7
UXMIP URB9 UBKD UERR UDOE UFE UPE
UART Status Register (USTAT)
6
The Parity Error bit indicates whether a parity
error is detected within a received character.
This bit is automatically cleared by the hard-
ware when the USTAT register is read.
0 – No parity error occurred.
1 – Parity error occurred.
The Framing Error bit indicates whether the
UART fails to receive a valid stop bit at the end
of a frame. This bit is automatically cleared by
the hardware when the USTAT register is
read.
0 – No framing error occurred.
1 – Framing error occurred.
The Data Overrun Error bit is set when a new
character is received and transferred to the
URBUF register before software has read the
previous character from the URBUF register.
This bit is automatically cleared by the hard-
ware when the USTAT register is read.
0 – No receive overrun error occurred.
1 – Receive overrun error occurred.
The Error Status bit indicates when a parity,
framing, or overrun error occurs (any time that
the UPE, UFE, or UDOE bit is set). It is auto-
matically cleared by the hardware when the
UPE, UFE, and UDOE bits are all 0.
0 – No receive error occurred.
1 – Receive error occurred.
The Break Detect bit indicates when a line
break condition occurs. This condition is de-
tected if RXD remains low for at least ten bit
times after a missing stop bit has been detect-
ed at the end of a frame. The hardware auto-
matically clears the UBKD bit upon read of the
USTAT register, but only if the break condition
on RXD no longer exists. If reading the USTAT
register does not clear the UBKD bit because
the break is still actively driven on the line, the
hardware clears the bit as soon as the break
condition no longer exists (when the RXD in-
put returns to a high level).
0 – No break condition occurred.
1 – Break condition occurred.
The Received 9th Data Bit holds the ninth
data bit, when the UART is configured to op-
erate in the 9-bit data format.
5
4
3
2
1
0
120
UXMIP
19.3.8
The UICTRL register is a byte-wide register that contains
the receive and transmit interrupt status bits (read-only bits)
and the interrupt enable bits (read/write bits). The register is
initialized to 01h at reset. The register format is shown be-
low.
UTBE
URBF
UDCTS
UCTS
UEFCI
UETI
UERI
UEEI UERI UETI UEFCI UCTS UDCTS URBF UTBE
7
UART Interrupt Control Register (UICTRL)
6
The Transmit In Progress bit indicates when
the UART is transmitting. The hardware sets
this bit when the UART is transmitting data
and clears the bit at the end of the last frame
bit.
0 – UART is not transmitting.
1 – UART is transmitting.
The Transmit Buffer Empty bit is set by hard-
ware when the UART transfers data from the
UTBUF register to the transmit shift register
for transmission. It is automatically cleared by
the hardware on the next write to the UTBUF
register.
0 – Transmit buffer is loaded.
1 – Transmit buffer is empty.
The Receive Buffer Full bit is set by hardware
when the UART has received a complete data
frame and has transferred the data from the
receive shift register to the URBUF register. It
is automatically cleared by the hardware
when the URBUF register is read.
0 – Receive buffer is empty.
1 – Receive buffer is loaded.
The Delta Clear To Send bit indicates whether
the CTS input has changed state since the
CPU last read this register.
0 – No change since last read.
1 – State has changed since last read.
The Clear To Send bit indicates the state on
the CTS input.
0 – CTS input is high.
1 – CTS input is low.
The Enable Flow Control Interrupt bit controls
whether a flow control interrupt is generated
when the UDCTS bit changes from clear to
set.
0 – Flow control interrupt disabled.
1 – Flow control interrupt enabled.
The Enable Transmitter Interrupt bit, when
set, enables generation of an interrupt when
the hardware sets the UTBE bit.
0 – Transmit buffer empty interrupt disabled.
1 – Transmit buffer empty interrupt enabled.
The Enable Receiver Interrupt bit, when set,
enables generation of an interrupt when the
hardware sets the URBF bit.
0 – Receive buffer full interrupt disabled.
1 – Receive buffer full interrupt enabled.
5
4
3
2
1
0