CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 121

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

UEEI
19.3.9
The UOVR register is a byte-wide, read/write register that
specifies the oversample rate. At reset, the UOVR register
is cleared. The register format is shown below.
UOVSR
19.3.10 UART Mode Select Register 2 (UMDSL2)
The UMDSL2 register is a byte-wide, read/write register that
controls the sample mode used to recover asynchronous
data. At reset, the UOVR register is cleared. The register
format is shown below.
USMD
7
7
UART Oversample Rate Register (UOVR)
Reserved
The Enable Receive Error Interrupt bit, when
set, enables generation of an interrupt when
the hardware sets the UERR bit in the USTAT
register.
0 – Receive error interrupt disabled.
1 – Receive error interrupt enabled.
The Oversampling Rate field specifies the
oversampling rate, as given in the following ta-
ble.
The USMD bit controls the sample mode for
asynchronous transmission.
0 – UART determines the sample position au-
1 – The USPOS register determines the sam-
tomatically.
ple position.
0000–0110
UOVSR3:0
Reserved
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
3
Oversampling Rate
UOVSR
1
16
10
11
12
13
14
15
7
8
9
USMD
0
0
121
19.3.11 UART Sample Position Register (USPOS)
The USPOS register is a byte-wide, read/write register that
specifies the sample position when the USMD bit in the
UMDSL2 register is set. At reset, the USPOS register is ini-
tialized to 06h. The register format is shown below.
USAMP
7
Reserved
The Sample Position field specifies the over-
sample clock period at which to take the first
of three samples for sensing the value of data
bits. The clocks are numbered starting at 0
and may range up to 15 for 16× oversampling.
The maximum value for this field is (oversam-
pling rate - 3). The table below shows the
clock period at which each of the three sam-
ples is taken, when automatic sampling is en-
abled (UMDSL2.USMD = 0).
The USAMP field may be used to override the
automatic selection, to choose any other clock
period at which to start taking the three sam-
ples.
Oversampling Rate
4
10
11
12
13
14
15
16
7
8
9
3
USAMP
Sample Position
1
2
2
3
3
4
4
5
5
6
6
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2
3
3
4
4
5
5
6
6
7
7
0
3
4
4
5
5
6
6
7
7
8
8