CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 4

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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3.0
The CP3BT10 connectivity processor is complete micro-
computer with all system timing, interrupt logic, program
memory, data memory, I/O ports included on-chip, making
them well-suited to a wide range of embedded applications.
The block diagram on page 1 shows the major on-chip com-
ponents of the CP3BT10.
3.1
The CP3BT10 implements the CR16C CPU core module.
The high performance of the CPU core results from the im-
plementation of a pipelined architecture with a two-bytes-
per-cycle pipelined system bus. As a result, the CPU can
support a peak execution rate of one instruction per clock
cycle.
For more information, please refer to the CR16C Program-
mer’s Reference Manual (document number 424521772-
101, which may be downloaded from National’s web site at
http://www.national.com).
3.2
The CP3BT10 supports a uniform linear address space of
up to 16 megabytes. Three types of on-chip memory occupy
specific regions within this address space:
The 256K bytes of Flash program memory are used to store
the application program, Bluetooth protocol stack, and real-
time operating system. The Flash memory has security fea-
tures to prevent unintentional programming and to prevent
unauthorized access to the program code. This memory
can be programmed with an external programming unit or
with the device installed in the application system (in-sys-
tem programming).
The 8K bytes of Flash data memory are used for non-vola-
tile storage of data entered by the end-user, such as config-
uration settings.
The 10K bytes of static RAM are used for temporary storage
of data and for the program stack and interrupt stack. Read
and write operations can be byte-wide or word-wide, de-
pending on the instruction executed by the CPU.
Up to 8M bytes of external memory can be added on an ex-
ternal bus. The external bus is only available on devices in
100-pin packages.
For Flash program and data memory, the device internally
generates the necessary voltages for programming. No ad-
ditional power supply is required.
3.3
The device has up to 37 software-configurable I/O pins, or-
ganized into five ports called Port B, Port C, Port G, Port H,
and Port I. Each pin can be configured to operate as a gen-
eral-purpose input or general-purpose output. In addition,
many I/O pins can be configured to operate as inputs or out-
puts for on-chip peripheral modules such as the UART, tim-
ers, or Microwire/SPI interface.
256K bytes of Flash program memory
8K bytes of Flash data memory
10K bytes of static RAM
Up to 8M bytes of external memory (100-pin devices)
Device Overview
CR16C CPU CORE
MEMORY
INPUT/OUTPUT PORTS
4
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push-
pull output, weak pull-up input, or high-impedance input.
3.4
The Bus Interface Unit (BIU) controls access to internal/ex-
ternal memory and I/O. It determines the configured param-
eters for bus access (such as the number of wait states for
memory access) and issues the appropriate bus signals for
each requested access.
The BIU uses a set of control registers to determine how
many wait states and hold states are used when accessing
Flash program memory, and the I/O area (Port B and Port
C). At start-up, the configuration registers are set for slowest
possible memory access. To achieve fastest possible pro-
gram execution, appropriate values must be programmed.
These settings vary with the clock frequency and the type of
off-chip device being accessed.
3.5
The ICU receives interrupt requests from internal and exter-
nal sources and generates interrupts to the CPU. An inter-
rupt is an event that temporarily stops the normal flow of
program execution and causes a separate interrupt handler
to be executed. After the interrupt is serviced, CPU execu-
tion continues with the next instruction in the program fol-
lowing the point of interruption.
Interrupts from the timers, UART, Microwire/SPI interface,
and Multi-Input Wake-Up, are all maskable interrupts; they
can be enabled or disabled by software. There are 32
maskable interrupts, assigned to 32 linear priority levels.
The highest-priority interrupt is the Non-Maskable Interrupt
(NMI), which is generated by a signal received on the NMI
input pin.
3.6
The integrated hardware Bluetooth Lower Link Controller
(LLC) complies to the Bluetooth Specification Version 1.1
and integrates the following functions:
3.7
The USB node is a Universal Serial Bus (USB) Node con-
troller compatible with USB Specification, 1.0 and 1.1. It in-
tegrates the required USB transceiver, the Serial Interface
Engine (SIE), and USB endpoint FIFOs. A total of seven
endpoint pipes are supported: one bidirectional pipe for the
mandatory control EP0 and an additional six pipes for unidi-
rectional endpoints to support USB interrupt, bulk, and iso-
chronous data transfers.
4.5K-byte dedicated Bluetooth data RAM
1K-byte dedicated Bluetooth Sequencer RAM
Support of all Bluetooth 1.1 packet types
Support for fast frequency hopping of 1600 hops/s
Access code correlation and slot timing recovery circuit
Power Management Control Logic
BlueRF-compatible interface to connect with National’s
LMX5252 and other RF transceiver chips
INTERRUPT CONTROL UNIT (ICU)
USB
BUS INTERFACE UNIT
BLUETOOTH LLC