CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 147
CP3BT10G38
Manufacturer Part Number
CP3BT10G38
Description
IC CPU RISC W/LLC&USB 100-LQFP
Manufacturer
National Semiconductor
Datasheet
1.CP3BT10G38.pdf
(210 pages)
Specifications of CP3BT10G38
Applications
Connectivity Processor
Core Processor
CR16C
Program Memory Type
FLASH (256 kB)
Controller Series
CP3000
Ram Size
10K x 8
Interface
Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
Number Of I /o
37
Voltage - Supply
2.25 V ~ 2.75 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*CP3BT10G38
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23.2.3
Mode 3 is the Dual Independent Timer mode, which gener-
ates system timing signals or counts occurrences of exter-
nal events.
Timer/Counter 1 (TCNT1) counts down at the rate of the se-
lected clock. On underflow, it is reloaded from the TCRA
register and counting proceeds down from the reloaded val-
ue. In addition, the TA pin is toggled on each underflow if this
function is enabled by the TAEN bit. The initial state of the
TA pin is software-programmable. When the TA pin is tog-
gled from low to high, it sets the TCPND interrupt pending
bit and also generates an interrupt if enabled by the TAIEN
bit.
Because the TA pin toggles on every underflow, a 50% duty
cycle PWM signal can be generated on the TA pin without
any further action from the CPU.
Mode 3: Dual Independent Timer/Counter
Timer 1
Timer 2
Clock
Clock
Figure 65. Dual-Independent Timer/Counter Mode
Timer/Counter 1
Timer/Counter 2
Reload A
Reload B
TCNT1
TCNT2
TCRA
TCRB
Underflow
Underflow
147
Figure 65 is a block diagram of the Multi-Function Timer
configured to operate in Mode 3. The timer is configured to
operate as a dual independent system timer or dual external
event counter. In addition, Timer/Counter 1 can generate a
50% duty cycle PWM signal on the TA pin.
Timer/Counter 2 (TCNT2) counts down at the rate of the se-
lected clock. On underflow, it is reloaded from the TCRB
register and counting proceeds down from the reloaded val-
ue. In addition, each underflow sets the TDPND interrupt
pending bit and generates an interrupt if the interrupt is en-
abled by the TDIEN bit.
TDPND
TAPND
TDIEN
TAIEN
TAEN
Timer
Interrupt 1
Timer
Interrupt 2
DS168
TA
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