PCA9620H/Q900/1,51 NXP Semiconductors, PCA9620H/Q900/1,51 Datasheet - Page 59

• Manufacturer Part Number: PCA9620H/Q900/1,51
• Description: LCD Drivers 480 SEGMENT LCD SEGMENT DRIVER
• Manufacturer: NXP Semiconductors

Specifications of PCA9620H/Q900/1,51

• Number Of Segments: 60
• Maximum Clock Frequency: 14500 Hz
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-80
• Maximum Supply Current: 200 uA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935291899518

NXP Semiconductors
12. Dynamic characteristics
Table 36.
V
specified.
[1]
[2]
[3]
[4]
[5]
PCA9620
Product data sheet
Symbol
f
f
t
t
Timing characteristics: I
f
t
t
t
t
t
t
t
t
t
C
t
t
t
t
osc
clk(ext)
clk(H)
clk(L)
SCL
BUF
HD;STA
SU;STA
VD;DAT
VD;ACK
LOW
HIGH
f
r
SU;DAT
HD;DAT
SU;STO
w(spike)
DD1
b
Internal calibration made with OTP so that the maximum variation is ±15 % over whole temperature and voltage range. The typical f
generates a typical frame frequency of 200 Hz when the default frequency division factor is used (see
The typical value is defined at V
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V
input voltage swing of V
t
t
VD;DAT
VD;ACK
= 2.5 V to 5.5 V; V
= minimum time for valid SDA output following SCL LOW.
= time for acknowledgement signal from SCL LOW to SDA output LOW.
Dynamic characteristics
Parameter
oscillator frequency
external clock frequency
HIGH-level clock time
LOW-level clock time
SCL frequency
bus free time between a
STOP and START condition
hold time (repeated) START
condition
set-up time for a repeated
START condition
data valid time
data valid acknowledge time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time
rise time
capacitive load for each bus
line
data set-up time
data hold time
set-up time for STOP
condition
spike pulse width
DD2
SS
2
C-bus
= 2.5 V to 5.5 V; V
to V
DD
DD1
[3]
.
= V
DD2
All information provided in this document is subject to legal disclaimers.
= 5.0 V and 30 °C.
SS
Conditions
on pin CLK; see
page 9
external clock source used
of both SDA and SCL signals
of both SDA and SCL signals
= 0 V; V
Rev. 1 — 9 December 2010
LCD
= 2.5 V to 9.0 V; T
Table 17 on
Universal LCD driver for low multiplex rates
amb
=
[1][2]
−
40
[4]
[5]
°
Min
8160
450
33
33
-
1.3
0.6
0.6
-
-
1.3
0.6
-
-
-
100
0
0.6
-
C to +105
Section 7.5.3 on page
Typ
9600
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
°
C; unless otherwise
PCA9620
© NXP B.V. 2010. All rights reserved.
IL
Max
11040
14500
-
-
400
-
-
-
0.9
0.9
-
-
0.3
0.3
400
-
-
-
50
and V
39).
IH
59 of 71
with an
Unit
Hz
Hz
μs
μs
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
ns
μs
ns
osc